E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022

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Document Table of Contents Auto Negotiation Config Register 6

Offset: 0xC6

Auto Negotiation Config Register 6 Fields

Bit Name Description Access Reset
31:0 user_next_page_high User Controlled AN Next page (upper bits)

[31:0]: Unformatted Code Field (or [47:16] when MP bit is low)

Note: When Consortium Next Page Send is enabled (consortium_next_page_send=1), the first two User Next Pages can be ignored and replaced with the Consortium Next Page sequence
RW 0x0