E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.3.5. Maximum TX Frame Size

Offset: 0x407

Maximum TX Frame Size Fields

Bit Name Description Access Reset
15:0 max_tx MAX_TX_SIZE_CONFIG

16 bits value that sets the maximum TX frame size. When TX frames exceed this size, the CNTR_TX_OVERSIZE statistic is incremented

  • After power-up, max_tx is set to 16'd9600
  • After i_csr_rst_n is asserted, max_tx is set to the value given by the module parameter tx_max_frame_size
RW 0x2580

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