E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.7.4.4. External Time-of-Day Module for Variations with 1588 PTP Feature

E-Tile Hard IP for Ethernet Intel® FPGA IP configurations that include the 1588 PTP module require an external time-of-day (TOD) module to provide a continuous flow of current time-of-day information. The TOD module must provide the entire 96 bits of time-of-day, in the V2 format, to avoid the reduced accuracy. You can instantiate the TOD module from the IP Catalog 3 and add it to your design. The TOD module updates the time-of-day output value on every clock cycle in the V2 format (96 bits).

When you generate a design example for your IP core with PTP variation, it includes the TOD module.

TOD Module Required Connections in 10G/25G Basic Mode or 100G PTP

When you select Basic Mode in the PTP Accuracy Mode under PTP Options, each 10G/25G Ethernet IP instance includes only one i_ptp_tod[95:0] port. For 1 to 4 10G/25G channels in the same E-Tile Hard IP for Ethernet IP core or 100G E-Tile Hard IP for Ethernet IP core, you need a single TOD IP and a single TOD Synchronizer IP. You cannot share the TOD IP with different E-Tile Hard IP for Ethernet IP core channels.

Table 13.  TOD Module Required Connections - 10G/25G Basic Mode or 100G PTPRequired connections for TOD module, listed using signal names of TOD modules. If you create your own TOD module it must have the output signals required by the E-Tile Hard IP for Ethernet Intel® FPGA IP. However, its signal names could be different than the TOD module signal names in the table.
TOD Module Signals Basic Mode Recommended Connections
clk Avalon® memory-mapped interface clock
rst_n Avalon® memory-mapped interface reset
period_clk o_clk_pll_div64 (PTP clock)

For more information, refer to Clocks section.

period_rst_n Global/system reset
time_of_day_96b[95:0] i_ptp_tod[95:0]

TOD Module Required Connections in 10G/25G Advanced Mode

When you select Advanced Mode in the PTP Accuracy Mode under PTP Options, each channel in a 10G/25G Ethernet IP instance contains two TOD IP interface ports, the i_sl_ptp_tx_tod[95:0] for TX port and the i_sl_ptp_rx_tod[95:0] for RX port. Each channel in the same 10G/25G E-Tile Hard IP for Ethernet IP core requires two TOD IPs and two TOD Synchronizer IPs.
Note: When reconfiguring between 10G and 25G data rate, each channel may require two additional TOD synchronizers to synchronize two different slaves TOD frequencies, 156.25 MHz frequency for 10G data rate and 390.625 MHz frequency for 25G data rate. Refer to the Clocks section for more details on clock connections and required frequencies.
Table 14.  TOD Module Required Connections - 10G/25G Advanced ModeRequired connections for TOD module, listed using signal names of TOD modules. If you create your own TOD module it must have the output signals required by the E-Tile Hard IP for Ethernet Intel® FPGA IP. However, its signal names could be different than the TOD module signal names in the table.
TOD Module Signals Advanced Mode Recommended Connections
TX TOD Module Signals
clk Avalon® memory-mapped interface clock
rst_n Avalon® memory-mapped interface reset
period_clk o_clk_pll_div66
period_rst_n Global/system reset
time_of_day_96b[95:0] i_sl_ptp_tx_tod[95:0]
RX TOD Module Signals
clk Avalon® memory-mapped interface clock
rst_n Avalon® memory-mapped interface reset
period_clk o_clk_rec_div66
period_rst_n Global/system reset
time_of_day_96b[95:0] i_sl_ptp_rx_tod[95:0]

For TOD Synchronizer IP connections, refer to the Ethernet Design Example Components User Guide.

3 The TOD module is located in the Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP.

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