E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.4.6. RX MAC Configuration

Offset: 0x50A

RX MAC Configuration Fields

Bit Name Description Access Reset
8 remove_rx_pad Remove PADs from padded frames

0: Padded frames are not altered

1: Pads are removed from padded frames
  • After power-on, remove_rx_pad defaults to 0
  • Afteri_csr_rst_n, remove_rx_pad is set to the value given by the parameter Bytes to remove from RX frames in the parameter editor.
RW 0x0
7 enforce_max_rx Enforce Maximum frame size on RX packets

0: Oversized frames are not altered

1: Frames are ended with FCS error if they exceed the programmed RX maximum frame size
  • After power on, this register defaults to 0
  • After i_csr_rst_n, this register is set to value of the parameter Enforce Maximum Frame Size in the parameter editor.
RW 0x0
4 en_strict_preamble Enable Strict Preamble Checking

0: Custom Preamble bytes are allowed between SOP and SFD

1: Packets are dropped if they do not have standard preamble bytes
  • After power-up, en_strict_preamble is set to 0
  • After i_csr_rst_n is asserted, en_strict_preamble is set to the value given by the parameter Enable strict preamble check in the parameter editor.
RW 0x0
3 en_check_sfd Enable Start Frame Delimiter Checking

0:Custom SFD bytes are allowed in preambles

1:Packets are dropped if they do not have a standard Start Frame Delimiter
  • After power-up, en_check_sfd is set to 0
  • After i_csr_rst_n is asserted, en_check_sfd is set to the value given by the parameter Enable strict SFD checking in the parameter editor.
RW 0x0
1 disable_rxvlan Disable RX VLAN detection

0: EHIP detects VLAN frames, counts them separately in stats, and marks them at EOP

1:EHIP ignores VLAN in RX data, and treats VLAN headers as payload bytes
  • At power-on, this register defaults to 0
  • When i_csr_rst_n is asserted, this register is set to the value given by the parameter RX VLAN detection in the parameter editor.
RW 0x0
0 en_plen Enable Packet Length Checking
1: EHIP asserts the length error bit of rx_error at EOP for Frames where the Type/Length field is a length, and the length advertised is greater than the length of the frame that was received
  • After power-on, en_plen is set to 1
  • After i_csr_rst_n,en_plen is set according to the module parameter rx_length_checking
RW 0x1

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