E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.11.10. Custom Rate Interface

The E-Tile Hard IP for Ethernet Intel FPGA IP Custom Rate Interface is available when you turn on Enable custom rate for 10G/25G channels in 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP variation. This parameter is not available when Enable SyncE With Dedicated Reference Clock Per Channel is turned on.

Note: Exposing custom rate cadence interface does not change the Ethernet operation. Ethernet protocol does not use this interface.
Note: Enabling this feature exposes the interface from Stratix® 10 E-Tile Transceiver Native PHY to the user. It does not enable a custom cadence feature within the E-Tile Hard IP for Ethernet. To enable the custom cadence feature in the Stratix® 10 E-Tile Transceiver Native PHY, you must set flowreg_rate register in the EHIP TX MAC Feature Configuration to 0x7.
Note: Refer to the E-Tile CPRI PHY IP for an example of the interface usage.
Table 44.  Signals of the Custom Rate InterfaceAll of the Custom Rate Interface signals except the i_sl_custom_cadence[ch-1:0] signal are asynchronous.

Signal Name

Width

Description

i_sl_custom_cadence[ch-1:0] 1

Custom data valid signal.

Connect this signal either to a counter that produces a steady data valid cadence that corresponds to the ratio between the clock rate used and the clock rate required, or a system that increases or decreases the data valid cadence based on the current occupancy of transceiver TX FIFO.

o_sl_txfifo_pfull[ch-1:0] 1

When asserted, indicates that the transceiver TX FIFO is partially full. At this point, the transceiver FIFO exceeds the programmed Partially Full watermark.

o_sl_txfifo_pempty[ch-1:0] 1

When asserted, indicates that the transceiver TX FIFO is partially empty. At this point, the transceiver FIFO is below the programmed Partially Full watermark.

o_sl_txfifo_overflow[ch-1:0] 1

When asserted, indicates that the transceiver TX FIFO has overflowed, and should be reset.

o_sl_txfifo_underflow[ch-1:0] 1

When asserted, indicates that the transceiver TX FIFO has underflowed, and should be reset.

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