E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.1.16. Consortium Next Page Override

Offset: 0xCD

Consortium Next Page Override Fields

Bit Name Description Access Reset
27:24 override_consortium_next_page_fec_control Override Consortium Next PAGE FEC Control

When Enable Consortium Next Page override is enabled (enable_consortium_next_page_override=1), this register overrides bits D27:D24 in the Unformatted Next Page with the following bits defined by the consortium:.

[24] = F1- CL91 RS-FEC ability

[25] = F2- CL74 RS-FEC ability

[26] = F3- CL91 RS-FEC request

[27] = F4- CL74 RS-FEC request

RW 0x0
19:0 override_consortium_next_page_tech Override Consortium Next Page Technology Ability

[8:0] = Override bits D8:D0 in the Unformatted Next Page from default of 0x003 to indicate extended technology abilities.

[19:9] = Override bits D26:D16 in the Unformatted Next Page with the following bits defined by the consortium:

  • [12:9] = Reserved, set to 0
  • [13] = 25GBASE-KR1 ability
  • [14] = 25GBASE-CR1 ability
  • [16:15] = Reserved, set to 0
  • [17] = 50GBASE-KR2 ability
  • [18] = 50GBASE-CR2 ability
RW 0x3

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