E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022
Document Table of Contents Enable RX Pause Frame Processing

Offset: 0x705

Enable RX Pause Frame Processing Fields

Bit Name Description Access Reset
7:0 en_rx_pause Enable Rx Pause
1:Enable PFC port for selected queue
  • After power-on, this reset is set to 0
  • After i_csr_rst_n, this register is set to a value given by the module parameter flow_control
RW 0x1

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