E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022

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Document Table of Contents PTP Reconfiguration Interfaces

When PTP is used, you access the control and status registers controlling the transceiver channels used for the PTP interface of the E-Tile Hard IP for Ethernet Intel FPGA IP during normal operation using an Avalon® memory-mapped interface.

The PTP reconfiguration interfaces are available when you use the 100G channel with 1 to 4 10G/25G channels, RS-FEC, and PTP variant.

Table 55.  PTP Reconfiguration InterfaceThe signals in this interface are clocked by the i_reconfig_clk clock and reset by i_reconfig_reset. Use the default AIB and transceiver configurations for PTP channels..
Note: Ports with a width including p are allocated 1 per PTP EMIB instance in the module.
Port Name Width Description


19 bits each lane

Control and status register address bus for PTP channel.



PTP channel write signal asserted to write data on reconfiguration write data bus.



PTP channel read signal asserted to start a read cycle.



PTP channel data to be written on a write cycle.



PTP channel data that was read by a read cycle.



Avalon® memory-mapped interface stalling signal for operations on PTP control and status registers in the respective channel. The read/write cycle is only complete when this signal goes low.