E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.9.5. TX and RX RS-FEC

If you turn on Enable RS-FEC in the E-Tile Hard IP for Ethernet Intel FPGA IP parameter editor, the IP core includes Reed-Solomon forward error correction (FEC) in both the receive and transmit datapaths. This feature is only available in 25G and 100G variants.
The IP core implements Reed-Solomon FEC per Clause 91 of the IEEE Standard 802.3bj. The Reed-Solomon FEC algorithm includes the following modules:
  • TX RS-FEC
    • 64b/66b to 256b/257b transcoding
    • High-Speed Reed-Solomon encoder
  • RX RS-FEC
    • Alignment marker lock
    • 256b/257b to 64b/66b transcoding
    • High-Speed Reed-Solomon decoder

Did you find the information on this page useful?

Characters remaining:

Feedback Message