E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.5.13. Lower 4 bytes of the Source address for Flow Control frames

Offset: 0x60F

Lower 4 bytes of the Source address for Flow Control frames Fields

Bit Name Description Access Reset
31:0 saddrl Lower 4 bytes of the Flow control Source Address
Lower 4 bytes of the 6 byte source address used for SFC and PFC frames
  • At power-on, saddrl is set to 32'hCBFC5ADD
  • After i_csr_rst_n is asserted, saddrl is set to the value given by module parameter tx_pause_saddr[31:0]
RW 0xCBFC5ADD

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