E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.2.12. Alignment Marker Lock

Offset: 0x328

Alignment Marker Lock Fields

Bit Name Description Access Reset
0 am_lock AM Lock

1: RX PCS has achieved Alignment Marker lock

Note: Not valid for single-lane EHIP
Note: Not valid when RS-FEC is enabled, Use the 0x180[0] register in the E-Tile Transceiver PHY UG to verify if the RX lanes are aligned. 33
RO 0x0
33 For more information on register 0x180 (rsfec_lanes_rx_stat), refer to the RS-FEC Registers map in the E-Tile Transceiver PHY UG.

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