E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.1.20. Link Training Config Register for Lane 0

Offset: 0xD3

Link Training Config Register for Lane 0 Fields

Bit Name Description Access Reset
26:16 lt_prbs_seed_ln0 Link Training PRBS Seed for Lane 0 (only applicable to 100G and 25G NRZ)

Sets the initial seed for PRBS. Default value is 11'h57e

RW 0x57E
2:0 lt_prbs_pattern_select_ln0 Link Training PRBS Pattern Select for Lane 0 (only applicable to 100G and 25G NRZ)

0: Use Clause 92 Polynomial 0

1: Use Clause 92 Polynomial 1

2: Use Clause 92 Polynomial 2

3: Use Clause 92 Polynomial 3

4: Use Clause 72 Polynomial (if CL72 PRBS parameter is enabled)

All other settings reserved

  • Default value for lane 0 is 0
RW 0x0

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