E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.2.23. Configuration Fields for TX PLD

Offset: 0x350

Configuration Fields for TX PLD Fields

Bit Name Description Access Reset
23 sel_50gx2 Select 100G mode
Selects whether EHIP receives EMIB data from 2 or 4 lanes
  • 0: Use 4 EMIB channels for data input
  • 1: Use 2 EMIB channels for data input
  • The TX datapath must be reset after changing this field
  • Not used for single lane channels (10G/25G)
  • Defaults to 0 after power up
  • After i_csr_rst_n, default value depends on the what you selected in the Select Ethernet Rate parameter.
    • When Select Ethernet Rate = 100G, sel_50gx2 = 0
RW 0x0
22 tx_deskew_clear EMIB Deskew clear
Reset signal for the TX PLD deskew logic.
  • 0: Normal deskew operation
  • 1: TX EMIB deskew circuit in reset
  • Defaults to 0 after power up and i_csr_rst_n
RW 0x0
21:16 tx_deskew_chan_sel Deskew channel select

Specifies which channels participate in the deskew procedure

  • For single lane channels (10G/25G)
    • Only used when single lane is in EHIP_MAC_PTP mode
    • [0]=1: include EHIP lane datapath EMIB in deskew; defaults to 1
    • [4]=1: include PTP EMIB from EHIP core in deskew; defaults to 1
  • After reset, defaults to 0
  • After i_csr_rst_n, default value depends on the Select Ethernet Rate parameter
  • For 100Gx4 channels
    • [0]=1: include EMIB0 in deskew; defaults to 1
    • [1]=1: include EMIB1 in deskew; defaults to 1
    • [2]=1: include EMIB2 in deskew; defaults to 1
    • [3]=1: include EMIB3 in deskew; defaults to 1
    • [4]=1: include EMIB4 in deskew; defaults to 1, only available in PTP mode
    • [5]=1: include EMIB5 in deskew; defaults to 1, only available in PTP mode
The TX datapath must be reset after changing values in this field.
RW 0x0
12:8 tx_fifo_afull TX FIFO almost full level

This is a debug feature that has been deprecated.

RW 0x0
2:0 tx_ehip_mode Portmap select

Selects how the synchronous input to the EHIP is mapped.

  • 3h0: MAC interface
  • 3h1: MAC interface with PTP
  • 3h2: PCS (MII) interface
  • 3h3: PCS66 interface with forced encoder and scrambler bypass
  • 3h4: PCS66 interface
  • 3'h5: Reserved
  • 3'h6: Reserved
  • 3'h7: PMA direct interface
  • After power up, defaults to 0
  • After i_csr_rst_n, default depends on the Select Ethernet IP Layers parameter
    • When Select Ethernet IP Layers = MAC+PCS, tx_ehip_mode = 3'd0
    • When Select Ethernet IP Layers = PCS-only, tx_ehip_mode = 3'd2
    • When Select Ethernet IP Layers = FlexE PHY, tx_ehip_mode = 3'd4
    • When Select Ethernet IP Layers= OTN PHY, tx_ehip_mode = 3'd3
The TX datapath must be reset after changing this field.
RW 0x0

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