E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.11.17.3.9. Single 25G Synchronous Ethernet Channel

External AIB Clocking Scheme

When Enable External AIB Clocking is enabled, external clock source can be used to drive TX and RX datapath. In this configuration, the Intel® Stratix® 10 10 E-Tile Transceiver Native PHY Intel FPGA IP in PLL mode can act as Channel PLL to drive i_aib_clk, i_sl_clk_tx and i_sl_clk_rx input clocks. The RX recovered clock (o_clk_rec_div66 or o_clk_rec_div64) can be fed to on-board clock cleaner. The filtered recovered clock should be connected to transceiver reference clock (i_clk_ref). The clock cleaner should also be configured to generate correct clock frequency for i_clk_ref.
Figure 68. Single Channel 25G SyncE with External AIB Clocking (FEC On)

Without External AIB Clocking Scheme

When Enable External AIB Clocking is disabled, i_sl_clk_tx and i_sl_clk_rx input clocks should be connected to output clock o_clk_pll_div64 (402.83MHz). Similarly, connect filtered and divided version of RX recovered clock (o_clk_rec_div64 or o_clk_rec_div66) to i_clk_ref.
Figure 69. Single Channel 25G SyncE without External AIB Clocking (FEC On)

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