E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Inter-Packet Gap Generation and Insertion

If you set Average Inter-packet Gap to 12 in the E-Tile Hard IP for Ethernet Intel FPGA IP parameter editor, the TX MAC maintains the minimum inter-packet gap (IPG) between transmitted frames required by the IEEE 802.3 Ethernet standard. The standard requires an average minimum IPG of 96 bit times (or 12 byte times). The MAC uses a deficit idle counter to allow the actual gap between frames to vary as needed to meet the maximum throughput requirements of the link.

If you set Average Inter-packet Gap to 10 or 8, the TX MAC maintains a minimum average IPG of 10 or 8 bytes accordingly. This option is provided as an intermediate option to allow you to enforce an IPG that does not conform to the Ethernet standard, but which increases the throughput of your IP core.

If you set Average Inter-packet Gap to 1, the IP core transmits Ethernet packets as soon as the data is available, with the minimum possible gap. The IPG depends on the space you leave between frame data as you write it to the core. If you select this parameter value, the core can no longer comply with the Ethernet standard, but your application can have control over the average gap and throughput can be maximized. For a packet of size (P) bytes, the number of idles bytes (G) inserted after is specified by the following formula G=8-(P%8). A few examples are depicted below:
Packet Size (P) Gap Idle Bytes (G)
64 8
65 7
66 6
67 5
68 4
69 3
70 2
71 1
72 8
Note: Even when you set the Average Inter-packet Gap to 1, the 10G/25G channels can still enforce an effective IPG of 5. This is because the protocol specifically prohibits IPG lower than 5 for 10G/25G links to prevent MACs from producing packets that cannot be encoded using 64B/66B encoders.