E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.10.1. Reset Sequence

The following waveforms shows the reset sequence using the i_csr_rst_n (100G)/i_sl_csr_rst_n (10G/25G), i_tx_rst_n (100G)/i_sl_tx_rst_n (10G/25G), and i_rx_rst_n (100G)/i_sl_rx_rst_n (10G/25G) signals.
Figure 35. External Hard Reset Sequence
Figure 36. TX Datapath Reset Sequence
Figure 37. RX Datapath Reset Sequence

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