E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals

All input signal names begin with i_ and all output signal names begin with o_.

Multi-channel signal names contain an array index [n] to the end of their name, where n= 0 to 3.

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