E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.11.16. Reset Signals

The IP core has three external hard reset inputs. These resets are asynchronous and are internally synchronized. In addition the IP core supports a dedicated reset signal that resets the transceiver and Ethernet reconfiguration interfaces but not the registers they control.

Assert the asynchronous resets for ten i_reconfig_clk cycles or until you observe the effect of their specific reset. Asserting the external hard reset i_csr_rst_n returns all Ethernet reconfiguration registers to their original values. o_rx_pcs_ready and o_tx_lanes_stable are asserted when the core has exited reset successfully.

Table 57.   Reset Signals All of the IP core reset signals except the i_reconfig_reset signal are asynchronous. The signal names are standard with slight differences to indicate the variations. For example:
  • For variants with single 10GE/25GE channel: i_sl_tx_rst_n
  • For variants with more than 1 channel: i_sl_tx_rst_n[n-1:0]
  • For variants with single 100E channel: i_tx_rst_n

Signal

Description

i_sl_tx_rst_n

i_sl_tx_rst_n[n-1:0]

i_tx_rst_n

Active-low hard reset signal.

Resets the TX interface, including the TX PCS and TX MAC. This reset leads to the deassertion of the o_tx_lanes_stable output signal.

i_sl_rx_rst_n

i_sl_rx_rst_n[n-1:0]

i_rx_rst_n

Active-low hard reset signal.

Resets the RX interface, including the RX PCS and RX MAC. This reset leads to the deassertion of the o_rx_pcs_ready output signal.

i_sl_csr_rst_n

i_sl_csr_rst_n[n-1:0]

i_csr_rst_n

Active-low hard global reset.

Resets the full IP core.

Resets the TX MAC, RX MAC, TX PCS, RX PCS, transceivers (transceiver reconfiguration registers and interface), and Ethernet reconfiguration registers. This reset leads to the deassertion of the o_tx_lanes_stable and o_rx_pcs_ready output signals.

i_reconfig_reset

Resets the E-Tile Hard IP for Ethernet Intel FPGA IP core Avalon® memory-mapped interfaces, both the transceiver reconfiguration interface and the Ethernet reconfiguration interface and some Ethernet soft registers..

This signal is synchronous with the i_reconfig_clk clock.

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