E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.9.2.8. 10G/25G TX and RX PTP Extra Latency

TX_PTP_EXTRA_LATENCY and RX_PTP_EXTRA_LATENCY registers define extra latency that IP core adds to the outgoing TX and the incoming RX timestamps. This time offset applies to all time values processed by the TX and RX PTP logic. It can be used to account for known errors on the PCB, or in other parts of the system.

According to IEEE 1588 PTP Standard, the timestamping point is the time when the first bit after the Start of Frame Delimiter (SFD) crosses Medium Dependent Interface (MDI). The TX and RX PTP Extra Latency calculation shown below only generates a timestamp when the SFD crosses the serial pin of an FPGA. To represent the time at the MDI, you should consider adding a delay of external PHY to the TX and RX PTP Extra Latency registers.

Table 24.  TX and RX PMA DelayThe table specifies transmitter and receiver PMA delay.
Configuration Datapath PMA Delay Constant

(in Hardware)

PMA Delay Constant

(in Simulation)

10G TX 105 105
RX 89 91
25G with and without RS-FEC TX 105 107
RX 89 94
100G with and without RS-FEC TX 105 107
RX 89 95

Steps to Calculate TX PTP Extra Latency

  1. Determine TX PMA delay from the TX and RX PMA Delay table.
  2. Calculate the TX PTP Extra Latency:
    • TX_PTP Extra Latency = TX PMA Delay * UI period (in ns)
  3. Write the calculated TX PTP Extra Latency to the TX_PTP_EXTRA_LATENCY register.

Steps to Calculate RX PTP Extra Latency

  1. Determine RX PMA delay from the TX and RX PMA Delay table.
  2. Calculate the RX PTP Extra Latency:

    RxCWPos represents a number of bit slips required to achieve RS-FEC alignment. Read PMA AVMM register 0x29[4:0] to obtain this value.

    RxBitSlip represents the number of bit slips required to achieve a block alignment.

    • RX PTP Extra Latency = -((RX PMA Delay + RxCWPos) * UI period (in ns)) for 25G with RS-FEC.
    • RX PTP Extra Latency = -((RX PMA Delay + RxBitSlip - 66) * UI period (in ns)) for 10G/25G without RS-FEC when RxBitSlip is greater than 62.
    • RX PTP Extra Latency = -((RX PMA Delay + RxBitSlip) * UI period (in ns)) for 10G and 25G without RS-FEC when RxBitSlip is smaller than or equal to 62.
  3. Write the calculated RX PTP Extra Latency to the RX_PTP_EXTRA_LATENCY register.

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