E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.1.1. ANLT Sequencer Config

Offset: 0xB0

ANLT Sequencer Config Fields

Bit Name Description Access Reset
31 kr_pause Pauses ANLT Function

1: Pauses ANLT function when kr_paused bit is high.

0: Normal ANLT function

Set this bit before accessing PMA registers via the transceiver reconfiguration interface to ensure no conflict with the ANLT function.

RW 0x0
29:26 anlt_seq_cfg_rxinv RX Polarity Inversion for Lane 0 to Lane 3
Sets RX Polarity Inversion on lanes 3:0 (for 100G NRZ), lanes 2 and 0 (for 100G PAM4) or current lane (for 25/10G).
  • [29] = Inverts RX PMA polarity on lane 3
  • [28] = Inverts RX PMA polarity on lane 2
  • [27] = Inverts RX PMA polarity on lane 1
  • [26] = Inverts RX PMA polarity on lane 0
RW 0x0
25:22 anlt_seq_cfg_txinv TX Polarity Inversion for Lane 0 to Lane 3
Sets TX Polarity Inversion on lanes 3:0 (for 100G NRZ), lanes 2 and 0 (for 100G PAM4) or current lane (for 25/10G).
  • [25] = Inverts TX PMA polarity on lane 3
  • [24] = Inverts TX PMA polarity on lane 2
  • [23] = Inverts TX PMA polarity on lane 1
  • [22] = Inverts TX PMA polarity on lane 0

Setting takes effect upon KR restart

RW 0x0
21 rsfec_request Request RS-FEC mode during AN

1: Request RS-FEC mode during AN

0: Do not request RS-FEC during AN

  • Defaults to 1 if parameter REQUEST_RSFEC is set to 1
  • This feature is new in E-Tile
RW 0x0
20 rsfec_capable Enables RS-FEC Negotiation

1: Enable RS-FEC negotiation

0: Do not negotiate for RS-FEC

Defaults to 1 if parameter ENABLE_RSFEC is set to 1
RW 0x0
19:16 anlt_seq_cfg_ilpbk Internal Loopback for Lane 0 to Lane 3
Sets internal loopback mode on lanes 3:0 (for 100G NRZ), lanes 0 and 2 (for 100G PAM4) or current lane (for 25/10G).
  • [16] = Internal loopback for lane 0
  • [17] = Internal loopback for lane 1
  • [18] = Internal loopback for lane 2
  • [19] = Internal loopback for lane 3

Loopback takes effect upon KR restart.

RW 0x0
14 skip_lt_on_an_timeout Skip Link Training on AutoNegotiation Timeout

1: If AN times out skip LT before attempting data mode, and use the previous LT settings

0: Use the normal ANLT sequence, even if link_fail_if_hiber = 0

  • This option is provided to speed up re-lock times when the link is known not to be resetting due to problems with link integrity
RW 0x0
13 link_fail_if_hiber Link Fail if HiBER

1: Trigger a link failure if a HiBER condition is detected in the PCS during data mode (default)

0: Ignore HiBER

RW 0x1
12 lt_failure_response Link Training Failure Response

1: Upon LT failure, PHY goes to data mode

0: Upon LT failure, PHY restarts AN, or if AN is disabled, skip AN and restart LT

RW 0x0
7:4 seq_force_mode Force the sequencer into a specific protocol, ignoring autonegotiation result

[6:4] = 3'b000: None

[6:4] = 3'b001: 25G-R1

[6:4] = 3'b010: Reserved

[6:4] = 3'b011: 100G-R4

[6:4] = 3'b100: Reserved

[6:4] = 3'b101: 10G-R1

[6:4] = 3'b110: Reserved

[6:4] = 3'b111: 100G-P2

[7] = 1'b1: Force RS-FEC on if capable (never for 10G, always for 100G-P2)

  • Forces the ANLT Sequencer into a specific protocol, ignoring the AN result
  • ANLT is still cycled if enabled; configure AN and LT using their respective CFG registers
Note: Not all protocols are available in all configurations. You must enable the protocols when generating the IP to be functional at run-time.
RW 0x0
2 disable_lf_timer Disable Link Fail Inhibit Timer

1: Disable the link fail inhibit timer

0: If PCS link fails, then AN restarts

  • The most common reason to disable the link fail inhibit timer is to characterize the link's behavior with link training
  • Turning off the link fail inhibit timer prevents link training from cycling, allowing each failure to be examined individually
  • Disabling the LFI Timer also disable transitioning from data mode to auto-negotiation phase when the link status goes down, even if the LFI timer has expired. Effectively the system stays in Data Mode state until reset or user intervention.
RW 0x0
1 disable_an_timer Disable Auto-Negotiation Timer

Enable this bit to allow operation with link partners that do not support auto-negotiation.

1: AN waits for valid partner without timing out (default). Auto-negotiation timeout is set to approximately 1 second.

0: If AN fails, the Sequencer tries a different protocol

RW 0x1
0 reset_seq Reset ANLT Sequencer

1: Reset only the ANLT Sequencer. Initiates a PCS reconfiguration or ANLT reset

0: Normal operation

This bit is self-cleared when the ANLT sequence restarts.

RW 0x0

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