E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Change in RX PCS Deskew Status

Offset: 0x329

lanes_deskewed Fields

Bit Name Description Access Reset
1 dskew_chng Change in deskewed status
1: RX PCS went from deskewed to not deskewed, or from not deskewed to deskewed
  • Not valid for single lane channels (10G/25G)
  • This bit is sticky. Use clr_frmerr to set this bit back to 0.
  • Resetting the RX datapath, or the entire core also clears the bit
RO 0x0
0 dskew_status Deskewed status

1: RX PCS is deskewed

0: RX PCS is not currently deskewed.

Note: There is some latency between this status bit and the actual state.
  • Not valid for single lane channels (10G/25G)
  • This bit is not sticky. Intel recommends that you replace this bit with a soft logic that can be made sticky based on the deskew_done port.
RO 0x0