E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

3.10.6. Status Interface for 64B/66B Line Rate

This section lists the status ports for the CPRI PHY 64b/66b line rate. Each CPRI PHY channel has its own status ports.
Table 100.  CPRI PHY Status Interface Signals for 64B/66B Interface
Port Name Width Domain Description
o_sl_tx_lanes_stable[n] 1 bit per channel Asynchronous The IP core asserts this signal to indicate that TX PMA is ready. The signal deasserts when i_csr_rst_n or i_tx_rst_n is deasserted.
o_sl_rx_pcs_ready[n] 1 bit per channel Asynchronous The IP core asserts this signal to indicate that the corresponding RX datapath is ready to receive data. The signal deasserts when i_csr_rst_n or i_rx_rst_n is deasserted.
o_sl_rx_block_lock[n] 1 bit per channel Asynchronous The IP core asserts this signal to indicate that 66b block alignment has completed for the corresponding CPRI PHY channel.
o_sl_rx_hi_ber[n] 1 bit per channel Asynchronous The IP core asserts this signal in accordance with IEEE 802.3 to indicate RX PCS is in Hi-Bit Error Rate (BER) state for the corresponding CPRI PHY channel.
o_sl_ehip_ready[n] 1 bit per channel Asynchronous The IP core asserts this signal after i_sl_csr_rst_n and i_sl_tx_rst_n is asserted to indicate that the CPRI PHY has completed all internal initialization, is ready to accept reconfiguration transactions and send data.

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