E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.2.27. Configuration for RX PCS

Offset: 0x360

Configuration for RX PCS Fields

Bit Name Description Access Reset
20 use_hi_ber_monitor Enable Hi-BER Monitor

0: Turn off Hi-BER monitor

1: Turn on Hi-BER monitor
  • The Hi-BER monitor is turned on by default because it is used for standard compliance
  • Hi-BER is needed to support Auto-Negotiation, and is generally used to report poor link conditions
  • When the Hi-BER monitor is turned on, if a Hi-BER condition is detected, the PCS replaces incoming data with Local Fault blocks
  • Disable the Hi-BER monitor if you need to monitor RX data while in a Hi-BER state
  • At power-on, this register defaults to 0
  • After i_csr_rst_n is asserted, the register is set to the value given by the hi_ber_monitor module parameter
RW 0x0
19:14 rx_pcs_max_skew Sets the maximum skew allowed by the RX PCS deskew logic
  • This parameter is set by default to the maximum safe limit for RX PCS deskew, which is higher than the value required by the Ethernet Standard
  • The max skew can be lowered for testing
  • Raising the max skew beyond the default can be dangerous, since some of the margin left by the limit is used to absorb dynamically changing induced skews due to the operation of the internal PCS logic
  • At power-on, this register defaults to 6'h3F
  • When i_csr_rst_n is asserted, this register is set to the value given by the rx_pcs_max_skew module parameter
RW 0x3F
13:0 am_interval Expected interval between Alignment markers per Virtual lane
  • This register is used only for multilane RX alignment. It is not used when RS-FEC is active, or for single lane channels
  • The interval is set by default to the number of valid blocks per virtual lane between alignment marker blocks required by the Ethernet Standard
  • For 100G links, RX alignment interval is TX alignment period/5
  • Alignment interval can be reduced to the time required to link (especially in simulation), but it is critical that both sides of the link have compatible AM spacing
  • The RX PCS must be reset using i_signal_ok, RX datapath reset, or RX PCS reset, after changing this register
  • At power-on, this is set to 14'h3FFF;
  • After i_csr_rst_n, if the module parameter sim_mode is enabled, this parameter is set to a sim mode value appropriate for the selected rate
  • After i_csr_rst_n, if the module parameter sim_mode is disabled, this parameter is set to mission mode value appropriate for the selected rate
RW 0x3FFF

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