E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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ID 683468
Date 12/28/2022
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP User Guide 2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core 3. About the E-Tile CPRI PHY Intel® FPGA IP 4. Supported Tools 5. E-tile Hard IP User Guide Archives
2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Supported Features 2.2. E-Tile Hard IP for Ethernet Intel FPGA IP Overview 2.3. IP Core Device Family and Speed Grade Support 2.4. IP Core Verification 2.5. Resource Utilization 2.6. Release Information 2.7. Getting Started 2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters 2.9. Functional Description 2.10. Reset 2.11. Interfaces and Signals 2.12. Register Descriptions 2.13. Document Revision History for the E-tile Hard IP for Ethernet Intel FPGA IP Core
2.3. IP Core Device Family and Speed Grade Support x
2.3.1. E-Tile Hard IP for Ethernet Intel FPGA IP Device Family Support 2.3.2. E-Tile Hard IP for Ethernet Intel FPGA IP Device Speed Grade Support
2.4. IP Core Verification x
2.4.1. Simulation Environment 2.4.2. Compilation Checking 2.4.3. Hardware Testing
2.7. Getting Started x
2.7.1. Installing and Licensing Intel® FPGA IP Cores 2.7.2. Specifying the IP Core Parameters and Options 2.7.3. Generated File Structure 2.7.4. Integrating Your IP Core in Your Design 2.7.5. IP Core Testbenches 2.7.6. Compiling the Full Design
2.7.1. Installing and Licensing Intel® FPGA IP Cores x
2.7.1.1. Intel® FPGA IP Evaluation Mode
2.7.4. Integrating Your IP Core in Your Design x
2.7.4.1. Channel Placement 2.7.4.2. Pin Assignments 2.7.4.3. Clock Requirements 2.7.4.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.4.5. SDC for Multiple E-Tile Instances
2.7.4.1. Channel Placement x
2.7.4.1.1. Guidelines and Restrictions for 24-bonded Channels Variant 2.7.4.1.2. Guidelines and Restrictions for 16-bonded Channels Variant
2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters x
2.8.1. Parameter Editor Parameters 2.8.2. RTL Parameters
2.9. Functional Description x
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC 2.9.2. 1588 Precision Time Protocol Interfaces 2.9.3. PCS, OTN, FlexE, and Custom PCS Modes 2.9.4. Auto-Negotiation and Link Training 2.9.5. TX and RX RS-FEC 2.9.6. PMA Direct Mode 2.9.7. Dynamic Reconfiguration 2.9.8. Ethernet Adaptation Flow for 10G/25G and 100G/4x25G Dynamic Reconfiguration Design Example 2.9.9. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example 2.9.10. Ethernet Adaptation Flow with PTP or with External AIB Clocking 2.9.11. Ethernet Adaptation Flow with Non-external AIB Clocking
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC x
2.9.1.1. MAC TX Datapath 2.9.1.2. MAC RX Datapath 2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 2.9.1.4. Pause Control and Generation Interface 2.9.1.5. Pause Control Frame Filtering 2.9.1.6. Link Fault Signaling 2.9.1.7. Order of Ethernet Transmission
2.9.1.1. MAC TX Datapath x
2.9.1.1.1. TX Preamble, Start, and SFD Insertion 2.9.1.1.2. Source Address Insertion 2.9.1.1.3. Length/Type Field Processing 2.9.1.1.4. Frame Padding 2.9.1.1.5. Frame Check Sequence (CRC-32) Insertion 2.9.1.1.6. Inter-Packet Gap Generation and Insertion
2.9.1.2. MAC RX Datapath x
2.9.1.2.1. RX Preamble Processing 2.9.1.2.2. RX Strict SFD Checking 2.9.1.2.3. RX FCS Checking 2.9.1.2.4. RX Malformed Packet Handling 2.9.1.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 2.9.1.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 2.9.1.2.7. Inter-Packet Gap
2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
2.9.1.3.1. Conditions Triggering XOFF Frame Transmission 2.9.1.3.2. Conditions Triggering XON Frame Transmission
2.9.1.6. Link Fault Signaling x
2.9.1.6.1. Determining Link Fault Condition
2.9.2. 1588 Precision Time Protocol Interfaces x
2.9.2.1. Implementing a 1588 System That Includes a E-Tile Hard IP for Ethernet Intel FPGA IP 2.9.2.2. PTP Timestamp Accuracy 2.9.2.3. PTP Transmit Functionality 2.9.2.4. PTP Receive Functionality 2.9.2.5. External Time-of-Day Module for 1588 PTP Variations 2.9.2.6. PTP Timestamp and TOD Formats 2.9.2.7. 10G/25G TX and RX Unit Interval Adjustment 2.9.2.8. 10G/25G TX and RX PTP Extra Latency 2.9.2.9. 100G PTP TX User Flow 2.9.2.10. 100G PTP RX User Flow 2.9.2.11. 100G RX Virtual Lane Offset Calculation for No FEC Variants 2.9.2.12. 100G UI Adjustment 2.9.2.13. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 2.9.2.14. PTP System Considerations 2.9.2.15. Logic Lock Regions Requirements for PTP Accuracy Advanced Mode
2.9.3. PCS, OTN, FlexE, and Custom PCS Modes x
2.9.3.1. PCS Only Mode 2.9.3.2. OTN Mode 2.9.3.3. FlexE Mode 2.9.3.4. Custom PCS Mode
2.10. Reset x
2.10.1. Reset Sequence
2.10.1. Reset Sequence x
2.10.1.1. Reset Sequence with External AIB Clocking
2.11. Interfaces and Signals x
2.11.1. TX MAC Interface to User Logic 2.11.2. RX MAC Interface to User Logic 2.11.3. TX PCS Interface to User Logic 2.11.4. RX PCS Interface to User Logic 2.11.5. FlexE and OTN Mode TX Interface 2.11.6. FlexE and OTN Mode RX Interface 2.11.7. TX Custom PCS Interface to User Logic 2.11.8. RX Custom PCS Interface to User Logic 2.11.9. PMA Direct Interface 2.11.10. Custom Rate Interface 2.11.11. Deterministic Latency Interface 2.11.12. 1588 PTP Interface 2.11.13. Ethernet Link and Transceiver Signals 2.11.14. Reconfiguration Interfaces and Signals 2.11.15. Miscellaneous Status and Debug Signals 2.11.16. Reset Signals 2.11.17. Clocks
2.11.14. Reconfiguration Interfaces and Signals x
2.11.14.1. Ethernet Reconfiguration Interfaces 2.11.14.2. Transceiver Reconfiguration Interfaces 2.11.14.3. RS-FEC Reconfiguration Interfaces 2.11.14.4. PTP Reconfiguration Interfaces
2.11.17. Clocks x
2.11.17.1. Asynchronous Adapter Clock in 10G/25G Mode 2.11.17.2. Asynchronous Adapter Clock in 100G Mode 2.11.17.3. Clock Network Use Cases
2.11.17.3. Clock Network Use Cases x
2.11.17.3.1. Single 25G Ethernet Channel (with FEC) 2.11.17.3.2. Single 10G Ethernet Channel (without FEC) 2.11.17.3.3. Four 25G Ethernet Channels (with FEC) within a Single FEC Block 2.11.17.3.4. Ethernet 25G x 4 (FEC Off) 2.11.17.3.5. 10G/25G Ethernet Channel with Basic PTP Accuracy Mode 2.11.17.3.6. 10G/25G Ethernet Channel with Advanced PTP Accuracy Mode 2.11.17.3.7. 100G Ethernet with Aggregated FEC 2.11.17.3.8. 100G Ethernet with PTP 2.11.17.3.9. Single 25G Synchronous Ethernet Channel 2.11.17.3.10. Multiple 25G Synchronous Ethernet Channels
2.12. Register Descriptions x
2.12.1. Auto Negotiation and Link Training Registers 2.12.2. PHY Registers 2.12.3. TX MAC Registers 2.12.4. RX MAC Registers 2.12.5. Pause and Priority- Based Flow Control Registers 2.12.6. TX Statistics Counter Registers 2.12.7. RX Statistics Counter Registers 2.12.8. 1588 PTP Registers 2.12.9. RS-FEC Registers 2.12.10. PMA Registers
2.12.1. Auto Negotiation and Link Training Registers x
2.12.1.1. ANLT Sequencer Config 2.12.1.2. ANLT Sequencer Status 2.12.1.3. Auto Negotiation Config Register 1 2.12.1.4. Auto Negotiation Config Register 2 2.12.1.5. Auto Negotiation Status Register 2.12.1.6. Auto Negotiation Config Register 3 2.12.1.7. Auto Negotiation Config Register 4 2.12.1.8. Auto Negotiation Config Register 5 2.12.1.9. Auto Negotiation Config Register 6 2.12.1.10. Auto Negotiation Status Register 1 2.12.1.11. Auto Negotiation Status Register 2 2.12.1.12. Auto Negotiation Status Register 3 2.12.1.13. Auto Negotiation Status Register 4 2.12.1.14. Auto Negotiation Status Register 5 2.12.1.15. AN Channel Override 2.12.1.16. Consortium Next Page Override 2.12.1.17. Consortium Next Page Link Partner Status 2.12.1.18. Link Training Config Register 1 2.12.1.19. Link Training Status Register 1 2.12.1.20. Link Training Config Register for Lane 0 2.12.1.21. Link Training Config Register for Lane 1 2.12.1.22. Link Training Config Register for Lane 2 2.12.1.23. Link Training Config Register for Lane 3
2.12.2. PHY Registers x
2.12.2.1. PHY Module Revision ID 2.12.2.2. PHY Scratch Register 2.12.2.3. Loopback Mode 2.12.2.4. PHY Configuration 2.12.2.5. Reset Sequencer RS-FEC Disable 2.12.2.6. RX CDR PLL Locked 2.12.2.7. TX Datapath Ready 2.12.2.8. Frame Errors Detected 2.12.2.9. Clear Frame Errors 2.12.2.10. RX PCS Status for AN/LT 2.12.2.11. PCS Error Injection 2.12.2.12. Alignment Marker Lock 2.12.2.13. Change in RX PCS Deskew Status 2.12.2.14. BER Count 2.12.2.15. Transfer Ready (AIB reset) Status for EHIP, ELANE, and PTP Channels 2.12.2.16. EHIP, ELANE, and RS-FEC Reset Status 2.12.2.17. PCS Virtual Lane 0 2.12.2.18. PCS Virtual Lane 1 2.12.2.19. PCS Virtual Lane 2 2.12.2.20. PCS Virtual Lane 3 2.12.2.21. Recovered Clock Frequency in KHz 2.12.2.22. TX Clock Frequency in KHz 2.12.2.23. Configuration Fields for TX PLD 2.12.2.24. Status for TX PLDs 2.12.2.25. Status for Dynamic Deskew Buffer 2.12.2.26. Configuration for RX PLD Block 2.12.2.27. Configuration for RX PCS 2.12.2.28. BIP Counter 0 2.12.2.29. BIP Counter 1 2.12.2.30. BIP Counter 2 2.12.2.31. BIP Counter 3 2.12.2.32. BIP Counter 4 2.12.2.33. BIP Counter 5 2.12.2.34. BIP Counter 6 2.12.2.35. BIP Counter 7 2.12.2.36. BIP Counter 8 2.12.2.37. BIP Counter 9 2.12.2.38. BIP Counter 10 2.12.2.39. BIP Counter 11 2.12.2.40. BIP Counter 12 2.12.2.41. BIP Counter 13 2.12.2.42. BIP Counter 14 2.12.2.43. BIP Counter 15 2.12.2.44. BIP Counter 16 2.12.2.45. BIP Counter 17 2.12.2.46. BIP Counter 18 2.12.2.47. BIP Counter 19 2.12.2.48. Timer Window for Hi-BER Checks 2.12.2.49. Hi-BER Frame Errors 2.12.2.50. Error Block Count 2.12.2.51. Deskew Depth 0 2.12.2.52. Deskew Depth 1 2.12.2.53. Deskew Depth 2 2.12.2.54. Deskew Depth 3 2.12.2.55. RX PCS Test Error Count
2.12.3. TX MAC Registers x
2.12.3.1. TX MAC Module Revision ID 2.12.3.2. TX MAC Scratch Register 2.12.3.3. Link Fault Configuration 2.12.3.4. IPG Words to remove per Alignment Marker Period 2.12.3.5. Maximum TX Frame Size 2.12.3.6. TX MAC Configuration 2.12.3.7. EHIP TX MAC Feature Configuration 2.12.3.8. TX MAC Source Address Lower Bytes 2.12.3.9. TX MAC Source Address Higher Bytes
2.12.4. RX MAC Registers x
2.12.4.1. RX MAC Module Revision ID 2.12.4.2. RX MAC Scratch Register 2.12.4.3. Maximum RX Frame Size 2.12.4.4. RX CRC Forwarding 2.12.4.5. Link Fault Status 2.12.4.6. RX MAC Configuration 2.12.4.7. EHIP RX MAC Feature Configuration
2.12.5. Pause and Priority- Based Flow Control Registers x
2.12.5.1. TXSFC Module Revision ID 2.12.5.2. TX SFC Scratch Register 2.12.5.3. Enable TX Pause Ports 2.12.5.4. TX Pause Request 2.12.5.5. Enable Automatic TX Pause Retransmission 2.12.5.6. Retransmit Holdoff Quanta 2.12.5.7. Retransmit Pause Quanta 2.12.5.8. Enable TX XOFF 2.12.5.9. Enable Uniform Holdoff 2.12.5.10. Set Uniform Holdoff 2.12.5.11. Lower 4 bytes of the Destination address for Flow Control 2.12.5.12. Higher 2 bytes of the Destination address for Flow Control 2.12.5.13. Lower 4 bytes of the Source address for Flow Control frames 2.12.5.14. Higher 2 bytes of the Source address for Flow Control frames 2.12.5.15. TX Flow Control Feature Configuration 2.12.5.16. Pause Quanta 0 2.12.5.17. Pause Quanta 1 2.12.5.18. Pause Quanta 2 2.12.5.19. Pause Quanta 3 2.12.5.20. Pause Quanta 4 2.12.5.21. Pause Quanta 5 2.12.5.22. Pause Quanta 6 2.12.5.23. Pause Quanta 7 2.12.5.24. PFC Holdoff Quanta 0 2.12.5.25. PFC Holdoff Quanta 1 2.12.5.26. PFC Holdoff Quanta 2 2.12.5.27. PFC Holdoff Quanta 3 2.12.5.28. PFC Holdoff Quanta 4 2.12.5.29. PFC Holdoff Quanta 5 2.12.5.30. PFC Holdoff Quanta 6 2.12.5.31. PFC Holdoff Quanta 7 2.12.5.32. RXSFC Module Revision ID 2.12.5.33. RXSFC Scratch Register 2.12.5.34. Enable RX Pause Frame Processing 2.12.5.35. Forward Flow Control Frames 2.12.5.36. Lower 4 bytes of the Destination address for RX Pause Frames 2.12.5.37. Higher 2 bytes of the Destination address for RX Pause Frames 2.12.5.38. RX Flow Control Feature Configuration
2.12.6. TX Statistics Counter Registers x
2.12.6.1. TX Statistics Registers
2.12.7. RX Statistics Counter Registers x
2.12.7.1. RX Statistics Registers
3. About the E-Tile CPRI PHY Intel® FPGA IP x
3.1. Supported Features 3.2. E-Tile CPRI PHY Intel® FPGA IP Overview 3.3. E-Tile CPRI PHY Device Family Support 3.4. Resource Utilization 3.5. Release Information 3.6. E-Tile CPRI PHY Intel FPGA IP Core Device Speed Grade Support 3.7. Getting Started 3.8. Parameter Settings 3.9. Functional Description 3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals 3.11. Registers 3.12. Document Revision History for the E-tile CPRI PHY Intel FPGA IP
3.7. Getting Started x
3.7.1. Installing and Licensing Intel® FPGA IP Cores 3.7.2. Specifying the IP Core Parameters and Options 3.7.3. Generated File Structure 3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement 3.7.5. IP Core Testbenches 3.7.6. Compiling the Full Design
3.7.1. Installing and Licensing Intel® FPGA IP Cores x
3.7.1.1. Intel® FPGA IP Evaluation Mode
3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement x
3.7.4.1. One 24.33024 Gbps channel with RS-FEC 3.7.4.2. Two 24.33024 Gbps Channel with RS-FEC 3.7.4.3. Three 24.33024 Gbps channels with RS-FEC 3.7.4.4. Four 24.33024 Gbps channels with RS-FEC 3.7.4.5. Restrictions
3.9. Functional Description x
3.9.1. CPRI PHY Functional Blocks 3.9.2. Dynamic Reconfiguration
3.9.1. CPRI PHY Functional Blocks x
3.9.1.1. E-tile Native PHY 3.9.1.2. Soft Reset Sequencer 3.9.1.3. Latency Measurement
3.9.1.3. Latency Measurement x
3.9.1.3.1. Deterministic Latency Calculation
3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals x
3.10.1. Clock Signals 3.10.2. TX MII Interface 3.10.3. RX MII Interface 3.10.4. TX 8B/10B Interface 3.10.5. RX 8B/10B Interface 3.10.6. Status Interface for 64B/66B Line Rate 3.10.7. Status Interface for 8B/10B Line Rate 3.10.8. Serial I/O Pins 3.10.9. Reconfiguration Interfaces (Avalon-MM)
3.10.9. Reconfiguration Interfaces (Avalon-MM) x
3.10.9.1. CPRI PHY Reconfiguration Interface 3.10.9.2. Transceiver Reconfiguration Interface 3.10.9.3. RS-FEC Reconfiguration Interface
3.11. Registers x
3.11.1. PHY Registers 3.11.2. CPRI PHY Registers 3.11.3. PMA Registers 3.11.4. RS-FEC Registers
3.11.3. PMA Registers x
3.11.3.1. Minimizing PMA Adaptation Time
4. Supported Tools x
4.1. E-Tile Channel Placement Tool 4.2. Ethernet Toolkit Overview 4.3. Document Revision History for the E-tile Channel Placement Tool and the Ethernet Link Inspector
4.2. Ethernet Toolkit Overview x
4.2.1. Features
1. About E-tile Hard IP User Guide
2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core
3. About the E-Tile CPRI PHY Intel® FPGA IP
4. Supported Tools
5. E-tile Hard IP User Guide Archives

2.13. Document Revision History for the E-tile Hard IP for Ethernet Intel FPGA IP Core

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.12.28 22.3 22.0.0 Corrected the default value for sim_mode
2022.09.26 22.3 22.0.0
  • Renamed the parameter Enable SyncE to Enable SyncE With Dedicated Reference Clock Per Channel
  • Added a table row for Disable ANLT Golden Recipe
  • Updated the "Conceptual Overview of General IP Core Reset Logic" table
2022.08.30 22.1 20.3.0

Corrected the IP version for Intel® Quartus® Prime Pro Edition software version 22.1 in the Release Information section

2022.07.01 22.1 20.3.0 Updated 1588 PTP Registers with the correct TXPTP_REVID and RXPTP_REVID in the 1588 PTP Registers table
2022.03.28 22.1 20.3.0 Made the following changes:
  • Updated section: Parameter Editor Parameters with the following:
    • Removed the note about 25G with PTP in section:
    • Added the Design Environment parameter to the E-Tile Hard IP for Ethernet Intel FPGA IP Parameters: IP Tab table
  • Updated section: Release Information with the following:
    • Added "IP-ETH-ETILEKRCR" to Ordering Codes to enable KR/CR (AN/LT) for E-Tile Ethernet Hard IP (10GE/25GE/100GE) in the IP Version in the E-Tile Hard IP for Ethernet Intel FPGA IP Core Release Information table
    • Added "IP-ETH-ETILEKRCR" to Ordering Codes to enable KR/CR (AN/LT) for E-Tile Ethernet Hard IP (10GE/25GE/100GE) in the IP Version in E-Tile Ethernet IP for Intel® Agilex™ FPGA Core Release Information table
2021.12.13 21.4 20.2.1 Made the following changes:
  • Added a clarifying note for Enable IEEE 1588 PTP and Enable external AIB clocking in section: Parameter Editor Parameters.
  • Corrected the default value of rx_pause_daddr in section: RTL Parameters,
  • Clarified the flowreg_rate register value for 10G variation.
  • Removed support for the NCSim simulator.
  • Added support for the QuestaSim* simulator.
2021.08.04 21.2 20.2.1 Made the following changes:
  • Corrected reset value for Lower 4 bytes of the Destination address for RX Pause Frames and Higher 2 bytes of the Destination address for RX Pause Frames.
  • Added SyncE support for 10G variant.
  • Added clarifying notes in section: PTP Timestamp and TOD Formats and PTP System Considerations.
  • Corrected descriptions for PHY Registers: Loopback Mode.
2021.03.29 21.1 20.2.1 Made the following changes:
  • Added a new section: SDC for Multiple E-Tile Instances.
  • Added a note about AN/LT in section: Parameter Editor Parameters.
  • Removed duplicate entries in Table: PTP Timestamp Accuracy per Ethernet Data Rate.
  • Added reset information while using the Ethernet Toolkit in section: Reset.
  • Updated description for Timer Window for Hi-BER Checks register.
  • Added new parameter: Enable SyncE.
  • Added new sections:
    • Single 25G Synchronous Ethernet Channel
    • Multiple 25G Synchronous Ethernet Channels
2020.12.14 20.4 20.2.1 Made the following changes:
  • Added new information for 100G PTP support.
  • Corrected the following figures:
    • Ethernet Cores Position on an E-tile Device
    • Ethernet 25G x 1
    • Ethernet 25G x 4 (FEC On) Master-Slave Configuration Option
  • Clarified the availability of asynchronous adapter clocks for 100G mode.
  • Added the PTP Accuracy Advanced Mode support for the Intel® Agilex™ devices.
  • Corrected the script location in section: Logic Lock Regions Requirements for PTP Accuracy Advanced Mode.
  • Added new register in PHY Registers: Reset Sequencer RS-FEC Disable.
  • Added new registers for 100G PTM PPM in section: 1588 PTP Registers.
2020.10.05 20.3 20.2.0 Made the following changes:
  • Added clarifying note regarding the Avalon® -ST interface modification in the E-Tile Hard IP for Ethernet Intel® FPGA IP. The note was added in the Client Interfaces for IP Core Variations table and the TX MAC Interface to User Logic section.
  • Added KDB link in the About the E-Tile Hard IP for Ethernet Intel® FPGA IP Core section.
  • Updated list of supported Ethernet channel protocols in the Ethernet Protocols table.
  • Updated External Time-of-Day Module for Variations with 1588 PTP Feature section. Added new subsections describing the PTP Accuracy modes:
    • TOD Module Required Connections in Basic Mode
    • TOD Module Required Connections in Advanced Mode
  • Updated the E-Tile Hard IP for Ethernet Intel® FPGA IP Parameters: IP Tab table:
    • Added PTP Accuracy Mode parameter.
  • Updated the E-Tile Hard IP for Ethernet Intel® FPGA IP Parameters: 10GE/25GE Tab:
    • Updated Enable asynchronous adapter clocks parameter description.
    • Added Include refclk_mux parameter.
  • Updated the E-Tile Hard IP for Ethernet Intel® FPGA IP Parameters: 100GE Tab table:
    • Added Preserve Unused Transceiver Channels parameter.
    • Added Reference Clock Frequency for Preserved Channels parameter.
  • Revised text in the Determining Link Fault Condition section. Removed outdated Intel® Quartus® Prime software version.
  • Updated PTP System Consideration topic.
  • Added new topics:
    • PTP Timestamp Accuracy
    • Logic Lock Regions Requirements for PTP Accuracy in Advanced Mode
  • Added links and updated adaptation flows with soft_tx_rst and soft_rx_rst resets in the following sections:
    • Ethernet Adaptation Flow for 10G/25G and 100G/4x25G Dynamic Reconfiguration Design Example
    • Ethernet Adaptation Flow with PTP or with External AIB Clocking
    • Ethernet Adaptation Flow with Non-external AIB Clocking
  • Updated Reset section:
    • Renamed reset from soft_sys_rst to eio_sys_rst in the Reset Signal Functions table.
    • Added soft_tx/rx_rst signals in the Reset Signal Functions table.
    • Removed i_rsfec_tx_rst_n/i_rsfec_rx_rst_n resets.
    • Revised System Consideration section. Included 10G/25G multi-channel master-slave configuration considerations.
  • Updated 1588 PTP Interface section to include the PTP accuracy mode feature. Revised and added new PTP accuracy mode related signals in the Signals of the Time of Day Interface table.
  • Updated i_clk_ref[n-1:0]/i_clk_ref signals description in the Transceiver Signals table.
  • Updated Clocks section:
    • Revised description of i_sl_clk_tx/rx and i_sl_clk_tx/rx[n] signals in the Clock Inputs table when PTP is enabled.
    • Revised description of i_sl_async_clk_tx[n] and i_sl_async_clk_rx[n] signals in the Clock Inputs table.
    • Added new signals: i_sl_tx_tod[n-1:0], i_sl_rx_tod[n-1:0], and i_clk_ptp_sample.
    • Revised description of the o_clk_pll_div64[n] signal in the Clock Outputs table.
    • Renamed section from 10G/25G Ethernet Channel with PTP, without External AIB Clocking to 10G/25G Ethernet Channel with Basic PTP Accuracy Mode. Added Basic PTP accuracy mode information.
    • Added new topic: 10G/25G Ethernet Channel with Advanced PTP Accuracy Mode.
  • Revised the Async FIFO description in the Clock Connection in Asynchronous FIFO Operation diagram.
  • Revised 0x326 and 0x328 registers description in the RX PCS Status for AN/LT section to include the RX alignment limitation.
  • Corrected the 0xB10 register width in the TX 1588 PTP Registers table.
2020.07.13 20.2 20.1.0 Made the following changes:
  • Corrected parallel clock frequency value for a 10GE data rate variant in the PTP Timestamp Accuracy per Ethernet Data Rate table. The frequency is 402.83 MHz.
  • Added i_reconfig_clk specific note in the Clock Inputs section. The note states that the clock is set to a higher frequency in the simulation of specified variants.
2020.06.29 20.2 20.1.0 Made the following changes:
  • Updated Debug and Testability feature in the E-Tile Hard IP for Ethernet Intel® FPGA IP Features section. Added support for the Ethernet Tool Kit.
  • Updated device family support in the E-Tile Hard IP for Ethernet Intel® FPGA IP Device Family Support table:
    • Intel® Stratix® 10 support moved from Preliminary to Final.
    • Intel® Agilex™ support moved from Advance to Preliminary.
  • Removed <your_ip>.regmap file from the IP Core Generated Files table. The file doesn't appear in the list of IP core generated files.
  • Updated External Time-of-Day Module for Variations with 1588 PTP Feature section.
  • Updated Average Inter-packet Gap description in the Intel® Agilex™ Parameters: IP Tab table and the Inter-Packet Generation and Insertion section.
  • Added clarifying note in the Include deterministic latency measurement interface description. in the IP Parameter section. This feature is for internal use only and should not be enabled.
  • Updated ReadyLatency description in the Intel® Agilex™ Parameters: 100GE Tab. Ready Latency parameter only supports MAC+PCS variant.
  • Updated RTL Parameters section to clarify the access to the RTL generated parameters in simulation and synthesis.
  • Removed 64-bit timestamp format from the following topics:
    • PTP Transmit Functionality
    • PTP Receive Functionality
    • External Time-of-Day Module for 1588 PTP Variations
    • PTP Timestamp and TOD Formats
  • Renamed and removed outdated signals in the PTP Transmit Block Diagram and the PTP Receive Block Diagram figures.
  • Updated the TX and RX PTP Extra Latency section:
    • Added text to inform user to consider SFD and MDI boundaries when calculating TX/RX PTP Extra Latency.
    • Added step to store the calculated TX/RX PTP Extra Latency in the TX/RX_PTP_EXTRA_LATENCY registers.
  • Added a note in the Deterministic Latency Interface section. This feature is for internal use only.
  • Updated signal descriptions in the 1588 PTP Interface section.
  • Added PTP clock assignments in the 10G/25G Ethernet Channel (with PTP and without External AIB Clocking) section.
  • Corrected eio_freq_lock description in the RX CDR PLL Locked register section. Corresponding physical lane's CDR are locked to data.
  • Removed text: The reset values in this table represents register values after a reset has completed. globally. Added the text in the Reconfiguration and Status Register Description section.
  • Added Loopback Mode register in the PHY Registers section.
2020.01.31 19.4 19.4.0 Made the following changes:
  • Updated Parameter Editor Parameters section:
    • Removed Reconfig clock rate parameter in the E-Tile Hard IP for Ethernet Intel® FPGA IP Parameters: IP Tab table.
    • Added Enable Dynamic RSFEC for KR parameter in the E-Tile Hard IP for Ethernet Intel® FPGA IP Parameters: IP Tab table.
    • Added Enable asynchronous adapter clocks parameter in the E-Tile Hard IP for Ethernet Intel® FPGA IP Parameters: 10GE/25GE Tab table.
    • Added Ready latency parameter in the E-Tile Hard IP for Ethernet Intel® FPGA IP Parameters: 10GE/25GE Tab table.
    • Added Enable asynchronous adapter clocks parameter in the E-Tile Hard IP for Ethernet Intel® FPGA IP Parameters: 100GE Tab table.
  • Updated the parallel clock frequency value to 161.132 MHz for 10GE data rate in the PTP Timestamp Accuracy per Ethernet Data Rate table.
  • Updated PTP Transmit Functionality section:
    • Added o_sl_ptp_ets_valid, o_sl_ptp_ets_fp[7:0], and o_sl_ptp_ets[95:0] signals in the Example Waveform for 2-step TX Timestamp using i_sl_ptp_ts_req Signal figure.
    • Added i_sl_ptp_cf_offset and i_sl_ptp_tx_its[95:0] signals in the Example Waveform for 1-step TX Timestamp using i_sl_ptp_ins_cf Signal figure.
    • Accurately updated all signal names.
  • Added new section: TX and RX PTP Extra Latency.
  • Updated o_sl_ptp_rx_its signal's width in the Example Waveform PTP Timestamp on RX PTP Interface figure.
  • Added link to the Ethernet Design Example Components User Guide in the PTP Timestamp and TOD Formats section.
  • Clarified the i_csr_rst_n/i_sl_csr_rst_n reset sequence in the Reset section.
  • Added clarifying notes in the Custom Rate Interface section.
  • Added clarifying notes in the Deterministic Latency Interface section.
  • Updated 1588 PTP Interface section:
    • Added comment clarifying 1-step and 2-step TX/RX timestamp interface signals behavior when Asynchronous mode is enabled.
    • Updated o_sl_tx_ptp_ready[n-1:0] and o_sl_rx_ptp_ready[n-1:0] signals description in the Signals of the PTP Status Interface table.
  • Updated text in the Miscellaneous Status and Debug Signals section.
  • Added three new adaptation flows:
    • Ethernet Adaptation Flow for 10G/25G and 100G/4x25G Dynamic Reconfiguration Design Example
    • Ethernet Adaptation Flow with External AIB Clocking and PTP
    • Ethernet Adaptation Flow with non-external AIB Clocking
  • Updated Clocks section.
    • Updated i_reconfig_clk clock frequency range to 100-125 MHz in the Clock Inputs table.
    • Updated description of i_sl_clk_tx/rx and i_sl_async_clk_tx/rx signals in the Clock Inputs table.
    • Added new section: Asynchronous Adapter Clock in 25G Mode.
    • Added new section: Asynchronous Adapter Clock in 100G Mode.
  • Updated Reset section:
    • Added Intel recommendation details on how to perform reset an IP.
    • Updated the i_csr_rst_n/i_tx_rsn_n, and i_rx_rsn_n signals for RX_FEC and TX_FEC blocks in the Reset Signals Function table
  • Updated Auto Negotiation and Link Training Registers section:
    • Added the rsfec_capable, rsfec_request, anlt_seq_cfg_txinv, and anlt_seq_cfg_rxinv signals in the ANLT Sequencer Config.
    • Added the enable_consortium_next_page_send, enable_consortium_next_page_receive, enable_consortium_next_page_override, ignore_consortium_next_page_tech_ability_code, and consortium_oui signals in the Auto Negotiation Config Register 1.
    • Added the an_next_page and consortium_oui_upper in the Auto Negotiation Config Register 2.
    • Added the consortium_next_page_received, consortium_negotiated_port_type, and rs_fec_negotiated in the Auto Negotiation Status Register.
    • Updated description of ieee_negotiated_port_type in the Auto Negotiation Status Register.
    • Added the user_next_page_low in the Auto Negotiation Config Register5.
    • Added new Auto Negotiation Config Register 6.
    • Updated the an_lp_adv_tech_a in the Auto Negotiation Status Register 5.
    • Updated AN Channel Override register description.
    • Updated description of override_consortium_next_page_tech and override_consortium_next_page_fec_control in the Consortium Next Page Override register.
    • Added new Consortium Next Page Link Partner Status register.
  • Updated flowreg_rate signal in the EHIP TX MAC Feature Configuration section.
2020.01.16 19.3 19.3.0 Made the following changes:
  • Updated tx_clkout and rx_clkout to 161.132 MHz in the Ethernet 25G x 4 (FEC On) Master-Slave Configuration: Dynamic Reconfiguration figure.
  • Updated legend with missing clocks in the Ethernet 25G x 4 (FEC On) Master-Slave Configuration: Dynamic Reconfiguration and Ethernet 25G x 4 (FEC On) Master-Slave Configuration: External AIB Clocking figures.
2019.12.30 19.3 19.3.0 Made the following changes:
  • Added 0x864 ~ 0x869 registers and their descriptions in the Reconfiguration and Status Register Descriptions: TX Statistics Registers section.
2019.11.15 19.3 19.3.0 Made the following changes:
  • Added Intel® Agilex™ device family support.
  • Added Ethernet Link Inspector in the E-Tile Hard IP for Ethernet Intel FPGA IP Features table.
  • Added note clarifying transceiver speed grade -3 support in the E-Tile Hard IP for Ethernet Intel FPGA IP Device Speed Grade Support.
  • Updated IP version, Intel® Quartus® Prime version, and release date in the E-tile Hard IP for Ethernet Intel FPGA IP Current Release Information table.
  • Updated parameters description in the Parameter Editor Parameters section:
    • Enable Auto-Negotiation on Reset
    • Link Fall Inhibit Time
    • Auto-Negotiation Master
    • Advertise both 10G and 25G during AN
    • Enable Link Training on Reset
  • Restructured 1588 Precision Time Protocol Interface section:
    • Updated the PTP Receive Block Diagram to include the RX and TX UI Adjustment block
    • Added new TX and RX Unit Interval Adjustment section
  • Updated PTP timestamp accuracy for 100GE in the PTP Timestamp Accuracy per Ethernet Data Rate table.
  • Updated ordering code from IP-ETH-ETILEHARDIP to IP-ETH-ETILEHIP in the E-tile Hard IP for Ethernet Intel FPGA IP Current Release Information table.
  • Renamed Guidelines and Restrictions section to Guidelines and Restrictions for 24-channel placement variant.
  • Added new section Guidelines and Restrictions for 16-channel placement variant.
  • Added clarification in PTP Transmit Functionality and PTP Receive Functionality sections stating that TX/RX PTP operations start only after the o_sl_rx/tx_ready signal is set.
  • Clarified statement on asserting the external hard reset in the Reset section.
  • Updated statement to include i_sl_tx_rst_n reset for 10G/25G variant in the Reset Sequence.
  • Reworded description of PTP registers in the 1588 PTP Interface section.
  • Updated registers description in the Deterministic Latency Interface section.
  • Updates signal's description in the Signals of the PTP Status Interface table.
  • Updated Reset Sequence with External AIB Clocking section.
  • Added new dynamic reconfiguration clock network use case in the Four 25G Ethernet Channels (with FEC) section.
  • Removed unclear statement from i_reconfig_reset description in the Reset Signals section.
  • Added clarification in the Auto-Negotiation and Link Training section: When enabled, link training supports the initial and continuous adaptation.
  • Added note to clarify that RX recovered clock is not available for PTP channels when PTP enabled, in the Clock Outputs table.
2019.09.18 19.2 19.2.0
  • Updated Variant Selection figure in the About the E-tile Hard IP for Ethernet Intel FPGA IP Core section.
    • Single 25G MAC with PCS and optional 1588PTP and (528,514) RS-FEC is not supported
    • 1 to 4-10GE/25G MAC with PCS and optional 1588PTP and (528,514) RS-FEC is not supported
  • Updated E-Tile Channel Placement Tool link in the Channel Placement section.
  • Updated Example Waveform PTP Timestamp on RX PTP Interface table in the PTP Receive Functionality table.
2019.08.07 19.2 19.2.0
  • Updated Variant Selection figure in the About the E-tile Hard IP for Ethernet Intel FPGA IP Core section.
  • Clarified comments in the MAC TX Datapath and the TX Preamble, Start, and SFD Insertion sections.
  • Removed MAC adapters support for the 100G channel in the E-Tile Hard IP for Ethernet Intel FPGA IP Overview and the Resource Utilization sections.
  • Updated the Release Information section.
  • Updated the Specifying the IP Core Parameters and Options section.
  • Added the Reset Sequence with External AIB Clocking section.
  • Updated the Clock Requirements section.
  • Updated the 100GE with RS FEC Variant section.
  • Added the Two Channels 100GE/25GE with RS-FEC and PTP Variant and the Three Channels 100GE/25GE with RS-FEC and PTP Variant sections.
  • Added link to Intel® Stratix® 10 Device Datasheet in the E-tile Hard IP for Ethernet Intel FPGA IP Device Speed Grade Support section.
  • Updated the Reconfig clock rate parameter description in the E-tile Hard IP for Ethernet Intel FPGA IP Parameters: IP Tab section.
  • Added reset information in the Four 25G Ethernet Channels (with FEC) within the Single FEC block - Master-Slave Configuration: Option 2 section.
  • Updated the Ethernet 25G x 4 (FEC Off) section.
  • Updated the 25G Ethernet Channel (with PTP and External AIB clocking) section.
  • Updated behavior of i_rx_rst_n signal in RX PCS and RX FEC blocks in the Reset Signal Functions table.
  • Renamed the PMA Register Base Addresses table with Transceiver Reconfiguration Interface Register Base Addresses name.
  • Added the PTP Reconfiguration Interface Register Base Addresses table.
  • Updated following bits in Auto Negotiation and Link Training Registers:
    • Removed RX polarity inversion for lane 0 to lane 3 signals anlt_seq_cfg_rxinv in ANLT Sequencer Config Fields register
    • Removed TX polarity inversion for lane 0 to lane 3 signals anlt_seq_cfg_txinv in ANLT Sequencer Config Fields register
    • Removed support for dynamic RS-FEC signals rsfec_request, rsfec_capable in ANLT Sequencer Config Fields register
    • Removed rs_fec_negotiated in Auto Negotiation Status Register
    • Removed consortium_next_page_received in Auto Negotiation Status Register
    • Updated override_an_tech_22_8, bits [23:19] in Auto Negotiation Config Register 5
    • Updated an_lp_adv_tech_a, bits [15:11] in Auto Negotiation Status Register 5
  • Added Minimizing PMA Adaptation Time section in the PMA Registers chapter.
  • Added Ethernet Link Inspector chapter.
2019.05.17 19.1 19.1
  • Added information for Custom PCS variations.
  • Added 1588 PTP feature support for 100G Ethernet rate variations.
  • Added information for external AIB clocking feature support.
  • Added the following parameters in Parameter Editor Parameters section:
    • RSFEC Clocking Mode
    • Enable external AIB clocking
    • Enable JTAG to Avalon Master Bridge
    • Number of PCS Channels in core
    • Custom PCS mode
    • RSFEC Fibre Channel(s) mode
    • Custom PCS Rate
    • PMA modulation type
    • PMA reference clock frequency
    • Enable custom rate regulation
  • Added 312.5 and 644.53125 MHz options for PHY Reference Frequency parameter in E-tile Hard IP for Ethernet Intel FPGA Parameters: 10GE/25GE Tab table.
  • Updated the width of the i_rsfec_reconfig_writedata and o_rsfec_reconfig_readdata RS-FEC reconfiguration signals to 8 bits.
  • Added the following PTP timestamp diagrams in PTP Transmit Functionality and PTP Receive Functionality:
    • Example Waveform for 2-step TX Timestamp using i_ptp_ts_req Signal
    • Example Waveform for 1-step TX Timestamp using i_ptp_ins_ets Signal
    • Example Waveform for for 1-step TX Timestamp using i_ptp_ins_cf Signal
    • Example Waveform PTP Timestamp on RX PTP Interface
  • Added PTP Timestamp Accuracy and Parallel Clock Frequency Support per Ethernet Data Rate table in Implementing a 1588 System That Includes a E-Tile Hard IP for Ethernet Intel FPGA IP Core section.
  • Removed the following diagrams from Implementing a 1588 System That Includes a E-Tile Hard IP for Ethernet Intel FPGA IP Core:
    • Example Ethernet System with Ordinary Clock Master and Ordinary Clock Slave
    • Hardware Configuration Example Using E-Tile Hard IP for Ethernet Intel FPGA IP in a 1588 System in Transparent Clock Mode
    • Software Flow Using Transparent Clock Mode System
    • Example Boundary Clock with One Slave Port and Two Master Ports
  • Added dynamic reconfiguration clock requirements to i_sl_clk_tx/i_sl_clk_tx[n] and i_sl_clk_rx/i_sl_clk_rx[n] in Clock Inputs table.
  • Added the following topics in the Clock Network Use Cases section:
    • 10G Ethernet Channel (with PTP and without External AIB Clocking)
    • 25G Ethernet Channel (with PTP and without External AIB Clocking)
    • 10G Ethernet Channel (with PTP and External AIB Clocking)
    • 25G Ethernet Channel (with PTP and External AIB Clocking)
  • Added RX recovered clock frequency for SyncE support in Clock Outputs table.
  • Added 10/25G Ethernet Channel (with PTP and without External AIB Clocking) and 10/25G Ethernet Channel (with PTP and External AIB Clocking) sections.
  • Added the following bits in Auto Negotiation and Link Training Registers:
    • seq_force_mode in ANLT Sequencer Config
    • anlt_seq_cfg_ilpbk in ANLT Sequencer Config
    • anlt_seq_cfg_txinv in ANLT Sequencer Config
    • anlt_seq_cfg_rxinv in ANLT Sequencer Config
    • kr_pause in ANLT Sequencer Config
    • high_effort_train in Link Training Config Register 1
    • train_start_initpre in Link Training Config Register 1
    • lt_cfg1_disable_rxcal in Link Training Config Register 1
    • lt_cfg1_disable_prxcal in Link Training Config Register 1
    • lt_cfg1_disable_prelt in Link Training Config Register 1
    • lt_cfg1_disable_postlt in Link Training Config Register 1
    • lt_cfg1_ovrd_lf in Link Training Config Register 1
    • lt_cfg1_ovrd_hf in Link Training Config Register 1
    • lt_cfg1_ovrd_bw in Link Training Config Register 1
    • restart_link_training_ln0 in Link Training Config Register 2
    • restart_link_training_ln2 in Link Training Config Register 2
    • restart_link_training_ln3 in Link Training Config Register 2
    • force_tx_nonce_value in Auto Negotiation Config Register 1
    • consortium_oui_upper in Auto Negotiation Config Register 2
  • Added AN Channel Override register.
  • Added Transfer Ready (AIB reset) Status for EHIP, ELANE, and PTP Channels register.
  • Added EHIP, ELANE, and RS-FEC Reset Status register.
  • Removed the following registers:
    • Reference Clock Frequency in KHz
    • Internal Error Vector for RX PCS
    • Internal Error Mask for RX PCS
  • Rebranded Altera Debug Master Endpoint to Native PHY Debug Master Endpoint in the E-Tile Hard IP for Ethernet Intel FPGA IP Parameters: IP Tab table.
2019.04.19 18.1.1 18.1.1 Updated RX Malformed Packet Handling section to clarify that packets with Error bytes are considered as malformed packets.
2019.01.11 18.1.1 18.1.1
  • Added RS-FEC support 25G and 100G Ethernet rate with PCS Only, OTN, and FlexE variations.
  • Updated the Variant Selection figure with new variations.
  • Updated the Resource Utilization for Selected Variations table.
  • Added the following parameters in the E-Tile Hard IP for Ethernet Intel FPGA IP Parameters table:
    • IEEE1588/PTP channel placement restriction
    • First RSFEC Lane
    • Request RSFEC
    • Advertise both 10G and 25G during AN
    • Enable Link Training on Reset
    • Enable Altera Debug Master Endpoint (ADME)
    • Ready latency
  • Added a note to clarify that TX MAC does not support non-contiguous packet transfers in MAC TX Datapath section.
  • Added TX and RX PCS datapath for RS-FEC variant block diagrams in TX PCS and RX PCS Datapath topic.
  • Added 1588 Precision Time Protocol Interfaces topic.
  • Added clock network use cases topic for the following use case:
    • Single 25G Ethernet channel with single FEC block
    • Single 10G Ethernet channel without FEC
    • Four 25G Ethernet channel with single FEC block
    • Four 25G Ethernet channel without FEC
    • 100G Ethernet channel with aggregate FEC
  • Added Guidelines and Restrictions topic to describe supported configurations for multi Native PHY channels with RS-FEC and optional PTP.
  • Added Channel Placement Guidelines and Restrictions.
  • Restructured Functional Description section into MAC, PCS/PCS66, PMA Direct Mode, Auto-Negotiation and Link Training, and TX and RX RS-FEC.
  • Added Determining Link Fault Condition.
  • Added reset sequences in Reset chapter.
  • Changed the following registers to reserved. These registers are not used in the IP core.
    • Asymmetric PTP Latency address 0xA0B
    • TX Extra Latency Information for PTP address 0xA0C
    • TX Extra Latency Information for PTP address 0xA0E
    • RX Extra Latency Information for PTP address 0xB07
    • RX Extra Latency Information for PTP address 0xB08
  • Removed PTP Asymmetric Latency feature support from E-Tile Hard IP for Ethernet Intel FPGA IP table. This feature is not supported in the IP.
2018.08.10 18.0 18.0 Initial release.
Level Two Title