E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022
Public
Document Table of Contents

2.7.6. Compiling the Full Design

You can use the Start Compilation command on the Processing menu in the Intel® Quartus® Prime Pro Edition software to compile your design.
Note: Intel does not guarantee timing closure, you may need to add extra timing constraint for your Ethernet Design. For additional timing constraint, refer to the E-Tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide or E-Tile Hard IP for Ethernet Intel Agilex FPGA IP Design Example User Guide.

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