E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.2.10. RX PCS Status for AN/LT

Offset: 0x326

RX PCS Status for AN/LT Fields

Bit Name Description Access Reset
1 hi_ber Hi-BER

1: One or more virtual lanes are in the Hi-BER state defined in the Ethernet specification

RO 0x0
0 rx_aligned RX PCS fully aligned

1: The RX PCS is fully aligned and ready to start decoding data

Note: Not valid when RS-FEC is enabled, Use the 0x180[0] register in the E-Tile Transceiver PHY UG to verify if the RX lanes are aligned. For more information on register 0x180 (rsfec_lanes_rx_stat), refer to the RS-FEC Registers map in the E-Tile Transceiver PHY UG.
RO 0x0

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