E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

3.10.7. Status Interface for 8B/10B Line Rate

This section lists the status ports for the CPRI PHY 8b/10b line rate. Each CPRI PHY channel has its own status ports.
Table 101.  CPRI PHY Status Interface Signals for 8B/10B Interface
Port Name Width Domain Description
o_sl_tx_ready[n] 1 bit per channel Asynchronous The IP core asserts this signal to indicate that TX is ready for the corresponding transceiver in PMA direct mode.
  • 1: TX ready
  • 0: TX not ready
o_sl_rx_ready[n] 1 bit per channel Asynchronous The IP core asserts this signal to indicate that RX is ready for the corresponding transceiver in PMA direct mode.
  • 1: RX ready
  • 0: RX not ready
o_sl_rx_patterndetect[n] 1 bit per channel o_rx_clkout2[n] The IP core asserts this signal to indicate that K28.5 has been detected in the current word boundary of o_sl_rx_d or o_sl_rx_c and the received data from the RX PMA achieved the word alignment.

This interface should be observed in conjunction with o_sl_rx_disperr and i_sl_rx_errdetect.

o_sl_rx_disperr[n] 2 bit per channel o_rx_clkout2[n] The IP core asserts this signal to indicate that it received 10-bit code or data group in the current word boundary of o_sl_rx_d or o_sl_rx_c has a disparity error.
  • Bit 0: Indicates status for lower data group.
  • Bit 1: Indicates status for higher data group.
o_sl_rx_errdetect[n] 2 bit per channel o_rx_clkout2[n] The IP core asserts this signal to indicate that it received 10-bit data group in the o_sl_rx_d or o_sl_rx_c has an 8b/10b code violation.
  • Bit 0: Indicates status for lower data group.
  • Bit 1: Indicates status for higher data group.

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