E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.12.1.7. Auto Negotiation Config Register 4

Offset: 0xC4

Auto Negotiation Config Register 4 Fields

Bit Name Description Access Reset
31:0 user_base_page_high User Controlled AN Base page (upper bits)

[31:30] = FEC bits

[29:5] = Technology Ability bits

[4:0] = TX Nonce bits

RW 0x0