E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

3.9.1.3.1. Deterministic Latency Calculation

The Deterministic Latency (DL) term used across this document refers to the ability to precisely determine the delay between the FPGA core and the PMA pins. Such delay varies from reset to reset and device to device. In most applications the variability is acceptable in order to determine the actual delay within a given reset. The below example shows the calculation delay between pins and FPGA core for the E-Tile CPRI PHY Intel FPGA IP.

The deterministic latency measurement methodology for Intel® Stratix® 10 and Intel® Agilex™ E-tile devices is based on the concept of measuring the time when a given word is at the interface to the PMA and when that same word is at the FPGA core. The difference in time between these two events, when added to the PMA propagation delay, determines the total latency between the FPGA core and the serial pins. Such a calculation intrinsically includes all delays due to intermediate logic, FIFOs and all other effects.

Table 91.  Deterministic Latency Measurement for Each Variant
Variant TX Delay (ns) RX Delay (ns)
2.4376/3.0720 Gbps TxDL * (sampling_clock_period in ns) / (2^8) + (365 * UI period in ns) RxDL * (sampling_clock_period) / (2^8) + (255 * UI period in ns) + (RxBitSlipL * UI period in ns)
4.9152/6.144/9.8304 Gbps TxDL * (sampling_clock_period in ns) / (2^8) + (367 * UI period in ns) RxDL * (sampling_clock_period) / (2^8) + (255 * UI period in ns) + (RxBitSlipL * UI period in ns)
10.1316/12.1651/24.33024 Gbps without RS-FEC TxDL * (sampling_clock_period in ns) / (2^8) + (569 * UI period in ns) RxDL * (sampling_clock_period) / (2^8) + (-347) * (UI period in ns) + (RxBitSlipH * UI period in ns)
10.1316/12.1651/24.33024 Gbps with RS-FEC TxDL * (sampling_clock_period in ns) / (2^8) + (537 * UI period in ns) RxDL * (sampling_clock_period) / (2^8) + (-315) * (UI period in ns) - (RxCwPos * UI period in ns)
The actual latency is a function of multiple factors. The following are the description of the usage of these factors to calculate the resulting TX and RX latencies.
Table 92.  Latency Calculation Description
Factor Description
TxDL Transmitter delay in sampling clock cycle. To calculate the TxDL value, read CPRI PHY register 0xC02 bit[20:0].

The register provides value in fixed point format. Bit[20:8] represents integer and bit[7:0] represents fractional number. For example, if bit[20:8] = 0x27 and bit [7:0] = 0xF4, the integer value is 39 and the fractional value is 0.953125 clock cycles. Therefore, the total delay is 39.953125 clock cycles.

Note: These values are available in the design example log file at \alt_cpriphy_c3_0_example_design\hardware_test_design\hwtest_sl\c3_cpri_test.log.
RxDL Receiver delay in sampling clock cycle. To calculate the RxDL value, read CPRI PHY register 0xC03 bit [20:0].

The register provides value in fixed point format. Bit[20:8] represents integer and bit[7:0] represents fractional number. For example, if bit[20:8] = 0x27 and bit [7:0] = 0xF4, the integer value is 39 and the fractional value is 0.953125 clock cycles. Therefore, the total delay is 39.953125 clock cycles.

Note: These values are available in the design example log file at \alt_cpriphy_c3_0_example_design\hardware_test_design\hwtest_sl\c3_cpri_test.log.
sampling_clock_period

For E-Tile CPRI PHY Intel FPGA IP, sampling clock is 250 MHz and the period is 4 ns.

RxBitSlipH37 Number of bit slip required to achieve block alignment for 10.1 Gbps or higher CPRI line rates without RS-FEC. Read PMA AVMM register 0x28[6:0] to obtain this value. This value is a constant per link up. This value is added to the RX latency calculation. It is assumed that the CPU aggregating the delays know the UI.
RxBitSlipL Number of bit slip required to achieve block alignment for 9.8 Gbps or lower CPRI line rates. Read CPRI AVMM register 0xC00[9:5] to obtain this value. This value is a constant per link up. This value is added to the RX latency calculation. It is assumed that the CPU aggregating the delays know the UI.
RxCwPos Number of bit slip required to achieve FEC alignment for 10.1 Gbps or higher CPRI line rates with RS-FEC. Read PMA AVMM register 0x29[4:0] to obtain this value. This value is a constant per link up. This value is added to the RX latency calculation. It is assumed that the CPU aggregating the delays know the UI.
37 If RxBitSlipH value is greater than or equal to 63, then the RxBitSlipH value is (66-RxBitSlipH). Else, the value is just RxBitSlipH.

Did you find the information on this page useful?

Characters remaining:

Feedback Message