E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.2.49. Hi-BER Frame Errors

Offset: 0x37B

Hi-BER Frame Errors Fields

Bit Name Description Access Reset
6:0 count Hi-BER Frame Errors

Sets the BER count that triggers hi_ber.

The Ethernet Standard (IEEE 802.3) defines the appropriate setting for ber_invalid_count based on rate.
  • 100GBASE-R4: 7'd97 (from Clause 82)
  • 25GBASE-R1: 7'd97 (from Clause 107)
  • 10GBASE-R1: 7'd16 (from Clause 49)

The RX PCS must be reset after changing this value.

RW 0x61

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