E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.10.1.1. Reset Sequence with External AIB Clocking

Below table shows the reset recommendation when the external AIB signal is used to reset the E-Tile Hard IP for Ethernet Intel FPGA IP data channels.

For details on general reset signals used during the reset, refer to Reset and Reset Signals sections.

Table 27.  External AIB Clocking Reset Signal FunctionsThis table is a reset sequence recommendation when external AIB clock is enabled. Signals marked by a tick (√) must be reset in the specified mode. Signals marked by a dash (—) don't required reset in the specified mode.
Modes Signals
i_csr_rst_n i_tx_rst_n i_rx_rst_n

External AIB clock enable —

Master Channel

26

External AIB clock enable —

Slave Channel

26

External AIB clock disable —

Master Channel

27

External AIB clock disable —

Slave Channel

27

Use case example with 10G Master Ethernet channel and three 25G Slave Ethernet channels is shown in the Master-Slave Configuration: Option 3- Dynamic Reconfiguration clock network use case section.

For more information on PMA Analog Reset user cases, refer to the E-tile Transceiver PHY User Guide.

For more information on the dynamic reconfiguration, refer to the Dynamic Reconfiguration Design Example User Guide.

26 If the External AIB clock is enabled, there is no need to assert i_csr_rst_n reset. If you assert this reset on the master channel after power on, it brings down slave channels.
27 This case has a limitation. i_csr_rst_n reset on the master channel brings down the slave channel.

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