E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.11.6. FlexE and OTN Mode RX Interface

The E-Tile Hard IP for Ethernet Intel FPGA IP RX client interface in FlexE and OTN variations employs the PCS66 interface protocol.

The FlexE and OTN variations allow the application to read 66b blocks from the RX PCS, bypassing the RX MAC.

The RX PCS acts as a source and the client acts as a sink in the receive direction.

Note: The E-Tile Hard IP for Ethernet Intel FPGA IP provides support for the OTN feature. For further inquiries, contact your nearest Intel sales representative.
Table 38.  Signals of the PCS66 RX InterfaceAll interface signals are clocked by the RX clock. The signal names are standard Avalon-ST signals with slight differences to indicate the variations. For example:
  • For variants with single 10GE/25GE channel: o_sl_rx_pcs66_d
  • For variants with more than 1 channel: o_sl_rx_pcs66_d[ch-1:0]
  • For variants with single 100GE channel: o_rx_pcs66_d

Name

Width

Description

o_sl_rx_pcs66_d

o_sl_rx_pcs66_d[ch-1:0]

o_rx_pcs66_d

66 (10G/25G)

264 (100G)

RX PCS 66b data for 1 block.

  • In FlexE mode, the RX PCS 66b data is aligned and descrambled but not decoded.
  • In OTN mode, the RX PCS 66b data is only aligned.

o_sl_rx_pcs66_valid

o_sl_rx_pcs66_valid[ch-1:0]

o_rx_pcs66_valid

1 When asserted, indicates that the RX PCS 66b data is valid.

o_sl_rx_pcs66_am_valid

o_sl_rx_pcs66_am_valid[ch-1:0]

o_rx_pcs66_am_valid

1 Alignment marker indicator.

When asserted, Indicates the blocks on the RX PCS 66b data signal are identified as RS-FEC codeword markers.

This signal is considered in OTN/FLEXE mode and is safe to ignore in other modes.

o_sl_rx_pcs_fully_aligned[n-1:0]

o_rx_pcs_fully_aligned

o_sl_rx_pcs_fully_aligned

1 bit for each channel Asserts when RX PCS is ready to receive data.
Figure 49. Receiving Data Using the PCS66 RX InterfaceThe figure shows how to read the 66b blocks directly from the RX PCS using the PCS mode RX Interface.

The 66b blocks follow Ethernet 64b/66b convention. The rightmost 2 bits of each 66 block is a 2b sync header and the remaining 64b are data.

  • In FlexE mode, the data is aligned and descrambled..
  • In OTN mode, the data is only aligned.

The data is only valid when o_rx_pcs66_valid is high. The contents of the o_rx_pcs66_d bus are not defined when o_rx_pcs66_valid is low.

The block order for the PCS66 mode RX interface is the same as the RX PCS interface. Blocks flow from right to left; the first block that the core receives is o_rx_pcs66_d[65:0].

The bit order for the PCS66 mode RX interface is the same as the RX PCS interface. Bits flow from right to left; the first bit that the core receives is o_rx_pcs66_d[0].

o_rx_pcs66_am_valid indicates the arrival of the alignment markers from the RX PCS. The alignment markers also depend on o_rx_pcs66_valid. When o_rx_pcs66_valid is low, o_rx_pcs66_am_valid is not valid.

  • In FlexE mode, when o_rx_pcs66_am_valid is high, o_rx_pcs66_d is undefined because the alignment markers do not get descrambled.
  • In OTN mode, when o_rx_pcs66_am_valid is high, o_rx_pcs66_d presents the received alignment markers.
Figure 50. Receiving Alignment Markers for FlexE Mode
Figure 51. Receiving Alignment Markers for OTN Mode

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