E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.2.50. Error Block Count

Offset: 0x37C

Error Block Count Fields

Bit Name Description Access Reset
31:0 count Error block count
  • Counts the number of Error blocks produced by the RX PCS Decoder
  • Valid only when the RX PCS Decoder is used and either alignment is achieved or alignment is not used and i_signal_ok = 1
  • Error blocks can be received from the remote link, or generated by violations of the Ethernet Standard 64B66B encoding specification
  • The counter is 32b wide and rolls over when the max count is reached
  • The counter's output can be frozen while still incrementing using i_snapshot or rx_shadow_req. Snapshot/rx_shadow_req is recommended for all reads, since the counter is wider than 1 byte
  • The counter is reset when i_signal_ok = 0, the RX datapath is reset, or the RX PCS is reset
RO 0x0

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