E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

3.10.8. Serial I/O Pins

The CPRI PHY IP core always includes the serial I/O pins. The simulation files use these pins to provide serial connections to the core and for synthesis to define the pin positions of the transceivers used by the core.
Table 102.  CPRI PHY Serial I/O Pins
Port Name Width Description
o_tx_serial[n] 1 bit per channel TX side transceiver serial pins. One for each channel.
i_rx_serial[n] 1 bit per channel RX side transceiver serial pins. One for each channel.

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