E-Tile Hard IP Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration
ID
683578
Date
5/05/2025
Public
2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. Multiple 25G Synchronous Ethernet Channels
2.3.6. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.7. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. CPRI Dynamic Reconfiguration Design Examples
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide
The E-tile Hard IP for Ethernet Intel® FPGA IP core for Stratix® 10 devices provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
In addition, you can download the compiled hardware design to the Stratix® 10 TX Transceiver Signal Integrity Development Kit. Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.
Data Rate | Variant | Simulation | Compilation-Only Project | Hardware Design Example |
---|---|---|---|---|
10GE | Single or multi channels Media Access Controller (MAC) + Physical Coding Sublayer (PCS) with optional 1588 Precision Time Protocol (PTP) | √ | √ | √ |
Single channel PCS | √ | √ | √ | |
Single channel Optical Transport Network (OTN) | √ | √ | X | |
Single channel Flexible Ethernet (FlexE) | √ | √ | X | |
Single or multi channels custom PCS | √ | √ | √ | |
25GE |
Single or multi channels MAC + PCS with optional RS-FEC and optional PTP
|
√ | √ | √ |
Single channel PCS with optional RS-FEC | √ | √ | √ | |
Single channel OTN with optional RS-FEC | √ | √ | X | |
Single channel FlexE with optional RS-FEC | √ | √ | X | |
Single or multi channels custom PCS with optional RS-FEC | √ | √ | √ | |
100GE | MAC+ PCS with optional:
|
√ | √ | √ |
MAC+PCS with (544, 514) RS-FEC | √ | √ | √ | |
PCS with optional (528,514) or (544, 514) RS-FEC | √ | √ | √ | |
OTN with optional (528,514) or (544, 514) RS-FEC | √ | √ | X | |
FlexE with optional (528,514) or (544, 514) RS-FEC | √ | √ | X |
Figure 1. Development Steps for the Design ExampleThe compilation-only example project cannot be configured in hardware.
Section Content
Directory Structure
Generating the Design
Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench
Compiling the Compilation-Only Project
Compiling and Configuring the Design Example in Hardware
Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example