E-Tile Hard IP Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

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ID 683578
Date 4/29/2024
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP Design Examples 2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example 3. E-tile CPRI PHY Intel® FPGA IP Design Example 4. E-Tile Dynamic Reconfiguration Design Example 5. E-tile Hard IP Stratix® 10 Design Examples User Guide Archives
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide 2.2. 10GE/25GE with Optional RS-FEC Design Examples 2.3. 100GE with Optional RS-FEC Design Example 2.4. Ethernet Toolkit Overview 2.5. Document Revision History for the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide x
2.1.1. Directory Structure 2.1.2. Generating the Design 2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench 2.1.4. Compiling the Compilation-Only Project 2.1.5. Compiling and Configuring the Design Example in Hardware 2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example
2.1.3. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench x
2.1.3.1. Fast Sim Model for E-tile Ethernet IP for Intel Stratix 10 FPGA
2.1.6. Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example x
2.1.6.1. 10GE/25GE Design Example 2.1.6.2. 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example 2.1.6.3. 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
2.2. 10GE/25GE with Optional RS-FEC Design Examples x
2.2.1. Simulation Design Examples 2.2.2. Hardware Design Examples 2.2.3. 10GE/25GE Design Example Interface Signals 2.2.4. 10GE/25GE Design Examples Registers
2.2.1. Simulation Design Examples x
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example 2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.2.2. Hardware Design Examples x
2.2.2.1. 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example Components 2.2.2.2. 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example Components 2.2.2.3. 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
2.3. 100GE with Optional RS-FEC Design Example x
2.3.1. Simulation Design Examples 2.3.2. Hardware Design Examples 2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals 2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals 2.3.5. Multiple 25G Synchronous Ethernet Channels 2.3.6. 100GE MAC+PCS with Optional RS-FEC Design Example Registers 2.3.7. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1. Simulation Design Examples x
2.3.1.1. Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example 2.3.1.2. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example 2.3.1.3. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example 2.3.1.4. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example 2.3.1.5. E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2. Hardware Design Examples x
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components 2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example 2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components 2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
2.4. Ethernet Toolkit Overview x
2.4.1. Features
3. E-tile CPRI PHY Intel® FPGA IP Design Example x
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide 3.2. E-tile CPRI PHY Design Example Description 3.3. Document Revision History for the E-tile CPRI PHY Intel® FPGA IP Design Example
3.1. E-tile CPRI PHY Intel® FPGA IP Quick Start Guide x
3.1.1. Hardware and Software Requirements 3.1.2. Generating the Design 3.1.3. Directory Structure 3.1.4. Simulating the Design Example Testbench 3.1.5. Compiling the Compilation-Only Project 3.1.6. Compiling and Configuring the Design Example in Hardware 3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
3.2. E-tile CPRI PHY Design Example Description x
3.2.1. Features 3.2.2. Simulation Design Example 3.2.3. Hardware Design Example 3.2.4. Interface Signals 3.2.5. Design Example Register Map for Reconfiguration
4. E-Tile Dynamic Reconfiguration Design Example x
4.1. Quick Start Guide 4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples 4.3. CPRI Dynamic Reconfiguration Design Examples 4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example 4.5. 100G Ethernet Dynamic Reconfiguration Design Example 4.6. Document Revision History for the E-Tile Dynamic Reconfiguration Design Example
4.1. Quick Start Guide x
4.1.1. Directory Structure 4.1.2. Generating the Design 4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench 4.1.4. Compiling and Configuring the Design Example in Hardware 4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example
4.1.2. Generating the Design x
4.1.2.1. Design Example Parameters
4.1.3. Simulating the E-Tile Dynamic Reconfiguration Design Example Testbench x
4.1.3.1. Running the Simulation 4.1.3.2. Generating New HEX File Using Eclipse-based Ashling RiscFree IDE Tool 4.1.3.3. Performing the Link Initialization
4.1.5. Testing the E-Tile Dynamic Reconfiguration Hardware Design Example x
4.1.5.1. Running the Design Example in Hardware 4.1.5.2. Power Management Setting for Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples x
4.2.1. Functional Description 4.2.2. Simulation Design Examples 4.2.3. Hardware Design Examples 4.2.4. 10GE/25GE Design Example Interface Signals 4.2.5. 10GE/25GE Design Examples Registers 4.2.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
4.2.1. Functional Description x
4.2.1.1. Clocking Scheme
4.2.2. Simulation Design Examples x
4.2.2.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Simulation Dynamic Reconfiguration Design Example Components 4.2.2.2. 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components
4.2.3. Hardware Design Examples x
4.2.3.1. 10GE/25GE MAC+PCS with RS-FEC and PTP Hardware Dynamic Reconfiguration Design Example Components 4.2.3.2. 10GE/25GE MAC+PCS with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.3. CPRI Dynamic Reconfiguration Design Examples x
4.3.1. Functional Description 4.3.2. Simulation Design Examples 4.3.3. Hardware Design Examples 4.3.4. CPRI Design Example Interface Signals 4.3.5. CPRI Design Example Registers 4.3.6. Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
4.3.1. Functional Description x
4.3.1.1. Clocking Scheme
4.3.2. Simulation Design Examples x
4.3.2.1. 24G CPRI PHY with RS-FEC Simulation Dynamic Reconfiguration Design Example Components 4.3.2.2. 9.8G CPRI PHY Simulation Dynamic Reconfiguration Design Example Components
4.3.3. Hardware Design Examples x
4.3.3.1. CPRI PHY with RS-FEC Hardware Dynamic Reconfiguration Design Example Components
4.4. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example x
4.4.1. Functional Description 4.4.2. Simulation Design Examples 4.4.3. Hardware Design Examples 4.4.4. 25G Ethernet to CPRI Design Example Interface Signals 4.4.5. 25G Ethernet to CPRI Design Examples Registers 4.4.6. Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
4.4.1. Functional Description x
4.4.1.1. Clocking Scheme 4.4.1.2. Reset
4.4.2. Simulation Design Examples x
4.4.2.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Simulation Dynamic Reconfiguration Design Example Components
4.4.3. Hardware Design Examples x
4.4.3.1. 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components
4.5. 100G Ethernet Dynamic Reconfiguration Design Example x
4.5.1. Functional Description 4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example 4.5.3. Simulation Design Examples 4.5.4. 100GE DR Hardware Design Examples 4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals 4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers 4.5.7. Steps to Enable FEC 4.5.8. Steps to Disable FEC
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example x
4.5.2.1. Dynamic Reconfiguration Flow in 100G Ethernet Dynamic Reconfiguration Example Design
4.5.3. Simulation Design Examples x
4.5.3.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Simulation Design Example 4.5.3.2. Simulating the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example Testbench
4.5.4. 100GE DR Hardware Design Examples x
4.5.4.1. 100GE MAC+PCS with Optional RS-FEC Dynamic Reconfiguration Hardware Design Example Components
4.5.7. Steps to Enable FEC x
4.5.7.1. Configuring for 100G NRZ with RSFEC [KR-FEC (528,514)] 4.5.7.2. Configuring for 100G NRZ with RSFEC [KP-FEC (544,514)] 4.5.7.3. Configuring for 100G PAM4 with RSFEC [KP-FEC (544,514)]
1. About E-tile Hard IP Design Examples
2. E-Tile Hard IP for Ethernet Intel FPGA IP Design Example
3. E-tile CPRI PHY Intel® FPGA IP Design Example
4. E-Tile Dynamic Reconfiguration Design Example
5. E-tile Hard IP Stratix® 10 Design Examples User Guide Archives

4.4.5. 25G Ethernet to CPRI Design Examples Registers

Table 42.   E-Tile Hard IP for Ethernet to CPRI Intel® FPGA IP Hardware Design Examples Register Map

Word Offset

Register Category

0x000000 – 0x000FFF Ethernet MAC and PCS registers
0x001000 – 0x001FFF Packet Generator and Checker registers
0x002000 – 0x002FFF PTP monitoring registers
0x010000 – 0x0107FF RS-FEC configuration registers
0x100000 – 0x1FFFFF Transceiver registers
0x003000 – 0x003FFF CPRI PHY soft registers
0x004000 – 0x004FFF Triple-speed Ethernet registers
0x006000 – 0x006FFF Triple-speed Ethernet traffic controller registers
Table 43.  Packet Client Registers You can customize the E-Tile Hard IP for Ethernet to CPRI Intel® FPGA IP hardware design example by programming the packet client registers.

Addr

Name

Bit

Description

HW Reset Value

Access

0x1000 PKT_CL_SCRATCH [31:0] Scratch register available for testing. N/A RW
0x1001 PKT_CL_CLNT [31:0] Four characters of IP block identification string CLNT. N/A RO
0x1008 Packet Size Configure [29:0] Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit[29:11]: Reserved.
  • Bit[10:0]: These bits specify the transmit packet size in bytes.
0x25800040 RW
0x1009 Packet Number Control [31:0] Specify the number of packets to transmit from the packet generator. 0xA RW
0x1010 PKT_GEN_TX_CTRL [7:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator disable bit. Set this bit to the value of 1 to turn off the packet generator, and reset it to the value of 0 to turn on the packet generator.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP core is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
  • Bit [5:4]:
    • 00: Reserved
    • 01: Fixed mode
    • 10: Reserved
  • Bit [6]: Set this bit to 1 to use 0x1009 register to turn off packet generator based on a fixed number of packets to transmit. Otherwise, bit[1] of PKT_GEN_TX_CTRL register is used to turn off the packet generator.
  • Bit [7]
    • 1: For transmission without gap in between packets.
    • 0: For transmission with random gap in between packets.
0x6 RW
0x1011 Destination address lower 32 bits [31:0] Destination address (lower 32 bits). 0x56780ADD RW
0x1012 Destination address upper 16 bits [15:0] Destination address (upper 16 bits). 0x1234 RW
0x1013 Source address lower 32 bits [31:0] Source address (lower 32 bits). 0x43210ADD RW
0x1014 Source address upper 16 bits [15:0] Source address (upper 16 bits). 0x8765 RW
Table 44.   CPRI PHY Soft Registers You can view the status ports and TX and RX datapath latencies of the CPRI PHY soft module by accessing the CPRI PHY registers.
Addr Name Bit Description HW Reset Value Access
0x3000 tunneling_enable [31] Datapath mode:
  • 0: LCA mode
  • 1: Tunneling mode
Note: You must set to 0 if the CPRI speed is not 10.1G, 9.8G, 4.9G, and 2.4G.
0x0 RW
rx_bitslip boundary_ sel [9:5] Indicates the number of bits that the 8B/10B RX PCS block slipped to achieve a deterministic latency. 0x0 RO
cpri_fec_en [4] Used by deterministic latency, this bit indicates whether the RS-FEC block is enabled.
  • [0]: Not enabled
  • [1]: Disabled
 0x1 RW
cpri_rate_ sel [3:0] Used by EFIFO and deterministic latency, this bit indicates the CPRI PHY and 1G Ethernet speed selection.
Bit [3:0]:
  • 0: Reserved
  • 1: 1GE
  • 2: 2.4G
  • 3: 3G
  • 4: 4.9G
  • 5: 6G
  • 6: 9.8G
  • 7 ~ 8: Reserved
  • 9: 10G
  • 10: 12G
  • 11: 24G
  • 12 ~ 15: Reserved
Note: The TX/RX datapath must be reconfigured after every setting change.
0xB RW
0x3001 dl_reset [1]

Deterministic Latency (DL) soft reset

Provides a soft reset to the DL block.
  • 0: DL block is not under reset.
  • 1: DL block is being reset.
Note: This is not a self-clearing reset.
0x0 RW
measure_ valid [0] Indicates whether the deterministic latency measurement values are valid.
  • 0: Not valid
  • 1: Valid
 0x0 RO
0x3002 tx_delay [20:0]

TX Datapath Latency

Displays the TX datapath deterministic latency measurement values measured in sampling_clk cycles.

measure_valid must be set prior taking the measurement.

0x0 RO
0x3003 rx_delay [20:0]

RX Datapath Latency

Displays the RX datapath deterministic latency measurement values measured in sampling_clk cycles.

measure_valid must be set prior taking the measurement.

0x0 RO
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