E-tile Hard IP for Ethernet Intel FPGA IP Release Notes
If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the
Quartus® Prime Design Suite Update Release Notes.
Added support for 10GE/25GE with
optional Reed-Solomon Forward Error Correction (RS-FEC) with
Auto-Negotiation and Link Training variant up to 4 channels.
Added support for Auto-Negotiation
and Link Training with the following features:
Optional RSFEC request during
Option to advertise copper cable (CR) or
backplane (KR) capability
Option to select default lane to perform
Option to advertise both 10GE and 25GE
capability during Auto-Negotiation
Option to enable symmetric and asymmetric
pauses as defined in Annex 28B of Section 2 of IEEE Std
Added support of the following
variants for 10GE/25GE:
Optical Transport Network (OTN)
Added Precision Timestamp Protocol
(PTP) for 10GE variant.
Added 156.250000 MHz PHY Reference
Frequency support for 10GE/25GE.
Added the following PHY Reference
Frequency support for 100GE:
Added support for RS-FEC (544,514)
coding for 100GE MAC + PCS, PCS only, OTN, and FlexE variants.
Added simulation and hardware design
examples for the following variants:
10GE/25GE/100GE MAC + PCS with optional RS-FEC
10GE/25GE PCS with optional RS-FEC and PTP
10GE/25GE OTN with optional RS-FEC and PTP
10GE/25GE FlexE with optional RS-FEC and
100GE PCS with optional RS-FEC
100GE OTN with optional RSF-FEC
100GE FlexE with optional RS-FEC
When there are multiple E-Tile for Hard IP Ethernet IP
cores with different configurations instantiated in a project, the
incorrectly or may cause fitter error.
Users will see compilation warning
where settings for modules with the same name are overwritten during
Quartus project compilation and design simulation compilation. This
may also affect the design functionality in simulation and