External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents

4.1.1. Intel Stratix 10 EMIF IP Interfaces for DDR3

The interfaces in the Intel Stratix 10 External Memory Interface IP each have signals that can be connected in Platform Designer. The following table lists the interfaces and corresponding interface types for DDR3.

Table 11.  Interfaces for DDR3
Interface Name Interface Type Description
local_reset_req Conduit Local reset request. Output signal from local_reset_combiner
local_reset_status Conduit Local reset status. Input signal to the local_reset_combiner
pll_ref_clk Clock Input PLL reference clock input
pll_locked Conduit PLL locked signal
pll_extra_clk_0 Clock Output Additional core clock 0
pll_extra_clk_1 Clock Output Additional core clock 1
pll_extra_clk_2 Clock Output Additional core clock 2
pll_extra_clk_3 Clock Output Additional core clock 3
oct Conduit On-Chip Termination (OCT) interface
mem Conduit Interface between FPGA and external memory
status Conduit PHY calibration status interface