External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public

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6.5.4.2. Layout Guidelines

The following table lists layout guidelines.

Unless otherwise specified, the guidelines in the following table apply to the following topologies:

  • DIMM—UDIMM topology
  • DIMM—RDIMM topology
  • DIMM—LRDIMM topology
  • Not all versions of the Intel® Quartus® Prime software support LRDIMM.
  • Discrete components laid out in UDIMM topology
  • Discrete components laid out in RDIMM topology

These guidelines are recommendations, and should not be considered as hard requirements. You should perform signal integrity simulation on all the traces to verify the signal integrity of the interface.

For supported frequencies and topologies, refer to the External Memory Interface Spec Estimator https://www.intel.com/content/www/us/en/programmable/support/support-resources/external-memory.html.

For frequencies greater than 800 MHz, when you are calculating the delay associated with a trace, you must take the FPGA package delays into consideration.

Table 211.  Layout Guidelines   (1)

Parameter

Guidelines

Decoupling Parameter

  • Make VTT voltage decoupling close to the components and pull-up resistors.
  • Connect decoupling caps between VTT and VDD using a 0.1F cap for every other VTT pin.
  • Use a 0.1 uF cap and 0.01 uF cap for every VDDQ pin.

Maximum Trace Length

  • Even though there are no hard requirements for minimum trace length, you need to simulate the trace to ensure the signal integrity. Shorter routes result in better timing.
  • For DIMM topology only:
    • Maximum trace length for all signals from FPGA to the first DIMM slot is 4.5 inches.
    • Maximum trace length for all signals from DIMM slot to DIMM slot is 0.425 inches.
  • For discrete components only:
    • Maximum trace length for address, command, control, and clock from FPGA to the first component must not be more than 7 inches.
    • Maximum trace length for DQ, DQS, DQS#, and DM from FPGA to the first component is 5 inches.

General Routing

  • Route over appropriate VCC and GND planes.
  • Keep signal routing layers close to GND and power planes.
Spacing Guidelines
  • Avoid routing two signal layers next to each other. Always make sure that the signals related to memory interface are routed between appropriate GND or power layers.
  • For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) for these traces. (Where H is the vertical distance to the closest return path for that particular trace.)
  • For Address/Command/Control traces: Maintain at least 3H spacing between the edges (air-gap) these traces. (Where H is the vertical distance to the closest return path for that particular trace.)
  • For Clock traces: Maintain at least 5H spacing between two clock pair or a clock pair and any other memory interface trace. (Where H is the vertical distance to the closest return path for that particular trace.)

Clock Routing

  • Route clocks on inner layers with outer-layer run lengths held to under 500 mils (12.7 mm).
  • Route clock signals in a daisy chain topology from the first SDRAM to the last SDRAM. The maximum length of the first SDRAM to the last SDRAM must not exceed 0.69 tCK for DDR3 and 1.5 tCK for DDR4. For different DIMM configurations, check the appropriate JEDEC* specification.
  • These signals should maintain the following spacings:
  • Clocks should maintain a length-matching between clock pairs of ±5 ps.
  • Clocks should maintain a length-matching between positive (p) and negative (n) signals of ±2 ps, routed in parallel.
  • Space between different pairs should be at least two times the trace width of the differential pair to minimize loss and maximize interconnect density.
  • To avoid mismatched transmission line to via, Intel® recommends that you use Ground Signal Signal Ground (GSSG) topology for your clock pattern—GND|CLKP|CKLN|GND.
  • Route all addresses and commands to match the clock signals to within ±20 ps to each discrete memory component. Refer to the following figure.

Address and Command Routing

  • Route address and command signals in a daisy chain topology from the first SDRAM to the last SDRAM. The maximum length of the first SDRAM to the last SDRAM must not be more than 0.69 tCK for DDR3 and 1.5 tCK for DDR4. For different DIMM configurations, chec