External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents Hard Memory Controller Features

Table 7.  Features of the Intel® Stratix® 10 Hard Memory Controller
Feature Description
Memory standards support
Supports the following memory standards:
Memory devices support Supports the following memory devices:
  • Discrete
3D Stacked Die support Supports 2 and 4 height of 3D stacked die for DDR4 to increase memory capacity.
Memory controller bypass mode You can use this configurable mode to bypass the hard memory controller and use your own customized controller.
Ping-Pong controller mode You can use this configurable mode to enable two memory controllers to time-share the same set of address and command pins.
Interface protocols support
  • Supports Avalon-MM interface.
  • The PHY interface adheres to the AFI protocol.
Rate support The hard memory controller runs at half rate. It can accept memory access commands from the core logic at half rate or quarter rate.
Configurable memory interface width Supports data widths from 8 to 72 bits, in 8 bit increments
Multiple ranks support Supports:
  • 4 ranks with single slot
  • 2 ranks with dual slots
Burst adapter

Able to accept burst lengths of 1–127 on the local interface of the controller and map the bursts to efficient memory commands. For applications that must strictly adhere to the Avalon® -MM specification, the maximum burst length is 64.

No burst chop support for DDR3 and DDR4.

Efficiency optimization features
  • Open-page policy—by default, opens page on every access. However, the controller intelligently closes a row based on incoming traffic, which improves the efficiency of the controller especially for random traffic.
  • Pre-emptive bank management—the controller issues bank management commands early, which ensures that the required row is open when the read or write occurs.
  • Data reordering—the controller reorders read/write commands.
  • Additive latency—the controller can issue a READ/WRITE command after the ACTIVATE command to the memory bank prior to tRCD, which increases the command efficiency.
User requested priority You can assign priority to commands. This feature allows you to specify that higher priority commands are issued earlier to reduce latency.
Starvation counter Ensures all requests are served after a predefined time out period, which ensures that low priority access are not left behind while reordering data for efficiency.
Timing for address/command bus

To maximize command bandwidth, you can double the number of memory commands in one controller clock cycle:

  • Quasi-1T addressing for half-rate address and command bus.
  • Quasi-2T addressing for quarter-rate address and command.
Note: Quasi-1T and Quasi-2T addressing is not supported for Ping Pong PHY.
Bank interleaving Able to issue read or write commands continuously to "random" addresses. You must correctly cycle the bank addresses.
On-die termination The controller controls the on-die termination signal for the memory. This feature improves signal integrity and simplifies your board design.
Refresh features
  • User-controlled refresh timing—optionally, you can control when refreshes occur and this allows you to prevent important read or write operations from clashing with the refresh lock-out time.
  • Per-rank refresh—allows refresh for each individual rank.
  • Controller-controlled refresh.
ECC support
  • 8 bit ECC code; single error correction, double error detection (SECDED).
  • User ECC supporting pass through user ECC bits as part of data bits.
DQS tracking Tracks the DQS timing and makes auto adjustments to align to the DQS edges.