External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022

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6.5.4. Design Layout Guidelines

The general layout guidelines in the following topic apply to DDR3 and DDR4 SDRAM interfaces.

These guidelines help you plan your board layout, but are not meant as strict rules that you must adhere to. Intel recommends that you perform your own board-level simulations to ensure that the layout you choose for your board allows you to achieve your desired performance.

For more information about how the memory manufacturers route these address and control signals on their DIMMs, refer to the Cadence PCB browser from the Cadence website, at www.cadence.com. You can find the various JEDEC* example DIMM layouts on the JEDEC* website, at www.jedec.org.

For assistance in calculating board skew parameters, refer to the board skew calculator tool, which you can find at the Intel website.

  1. The following layout guidelines include several +/- length based rules. These length based guidelines are for first order timing approximations if you cannot simulate the actual delay characteristic of the interface. They do not include any margin for crosstalk.
  2. To ensure reliable timing closure to and from the periphery of the device, you should register signals to and from the periphery before you connect any further logic.

Intel recommends that you get accurate time base skew numbers for your design when you simulate the specific implementation.