External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022

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Document Table of Contents Eye Diagram

The Generate Eye Diagram feature allows you to create read and write eye diagrams for each pin in your memory interface.

The Generate Eye Diagram feature uses calibration data patterns to determine margins at each Vref setting on both the FPGA pins and the memory device pins. A full calibration is done for each Vref setting. Other settings, such as DQ delay chains, will change for each calibration. At the end of a Generate Eye Diagram command, a default calibration is run to restore original behavior

The Generate Eye Diagram feature is available for DDR4 and QDR-IV protocols.