External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents

9.1.7. Intel Stratix 10 EMIF IP QDR-IV Parameters: Diagnostics

Table 305.  Group: Diagnostics / Simulation Options
Display Name Description
Calibration mode Specifies whether to skip memory interface calibration during simulation, or to simulate the full calibration process.

Simulating the full calibration process can take hours (or even days), depending on the width and depth of the memory interface. You can achieve much faster simulation times by skipping the calibration process, but that is only expected to work when the memory model is ideal and the interconnect delays are zero.

If you enable this parameter, the interface still performs some memory initialization before starting normal operations. Abstract PHY is supported with skip calibration.

Abstract phy for fast simulation Specifies that the system use Abstract PHY for simulation. Abstract PHY replaces the PHY with a model for fast simulation and can reduce simulation time by 3-10 times. Abstract PHY is available for certain protocols and device families, and only when you select Skip Calibration. (Identifier: DIAG_QDR4_ABSTRACT_PHY)
Show verbose simulation debug messages This option allows adjusting the verbosity of the simulation output messages. (Identifier: DIAG_QDR4_SIM_VERBOSE)
Table 306.  Group: Diagnostics / Calibration Debug Options
Display Name Description
Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port Specifies the connectivity of an Avalon slave interface for use by the Quartus Prime EMIF Debug Toolkit or user core logic.

If you set this parameter to "Disabled", no debug features are enabled. If you set this parameter to "Export", an Avalon slave interface named "cal_debug" is exported from the IP. To use this interface with the EMIF Debug Toolkit, you must instantiate and connect an EMIF debug interface IP core to it, or connect it to the cal_debug_out interface of another EMIF core. If you select "Add EMIF Debug Interface", an EMIF debug interface component containing a JTAG Avalon Master is connected to the debug port, allowing the core to be accessed by the EMIF Debug Toolkit.

Only one EMIF debug interface should be instantiated per I/O column. You can chain additional EMIF or PHYLite cores to the first by enabling the "Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option for all cores in the chain, and selecting "Export" for the "Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port" option on all cores after the first.

Enable Daisy-Chaining for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port