Visible to Intel only — GUID: jlb1606925012141
Ixiasoft
Visible to Intel only — GUID: jlb1606925012141
Ixiasoft
13.9.4. Configuration and Status Registers
Configuration registers that govern the resulting traffic pattern affect one of the following aspects of the pattern:
- Test duration / Instruction pattern
- Address pattern
- Data pattern
Symbol Address | Register Name | Register Width | Number of Registers | Readable or Writeable | Register Section | Register Description |
---|---|---|---|---|---|---|
0x0 | TG_VERSION | 32 | 1 | Readable | N/A | Version number of the traffic generator address map. |
0x4 | TG_START | 1 | 1 | Writeable | N/A | Perform a write to this register to start the traffic generator (any value). |
0x8 | TG_LOOP_COUNT | 32 | 1 | Readable and Writeable | Test Duration/Instruction Pattern | The number of read/write loops to run. A loop is defined as a block of writes followed by a block of reads. If this value is set to 0, the traffic generator will run infinite loops. |
0xC | TG_WRITE_COUNT | 12 | 1 | Readable and Writeable | Test Duration/Instruction Pattern | The number of unique writes to perform in each loop. |
0x10 | TG_READ_COUNT | 12 | 1 | Readable and Writeable | Test Duration/Instruction Pattern | Number of unique reads to perform in each loop. |
0x14 | TG_WRITE_REPEAT_COUNT | 16 | 1 | Readable and Writeable | Test Duration/Instruction Pattern | Number of times to repeat each write operation. |
0x18 | TG_READ_REPEAT_COUNT | 16 | 1 | Readable and Writeable | Test Duration/Instruction Pattern | Number of times to repeat each read operation. |
0x20 | TG_CLEAR | 4 | 1 | Readable and Writeable | Status | Clears the failure status registers. Allows clearing these registers independently from one another by writing a 1 to the following bits. BIT0 - Clears the recorded PNF data. BIT1 - Clears the recorded number of Avalon reads. BIT2 - Clears the recorded data of the first failure (address, expected data, and actual data). BIT3 - Clears the recorded data of address overflow due to burst length (last address written to, failure status). |
0x1C | TG_BURST_LENGTH | 7 | 1 | Readable and Writeable | Test Duration/Instruction Pattern | Avalon burst length. |
0x38 | TG_RW_GEN_IDLE_COUNT | 16 | 1 | Readable and Writeable | Test Duration/Instruction Pattern | Number of cycles for which the traffic generator remains idle between a write block and the next read block. |
0x3C | TG_RW_GEN_LOOP_IDLE_COUNT | 16 | 1 | Readable and Writeable | Test Duration/Instruction Pattern | Number of cycles for which the traffic generator remains idle between a read block and the next write block. |
0x40 | TG_SEQ_START_ADDR_WR | 32 | 12 | Readable and Writeable | Address Pattern | Start address for writes; used as a seed address in Random and Fixed Modes. Consists of 12 registers, 2 for each address field.[CS1] Each pair of adjacent registers represents the lower 32 bits and upper 32 bits of a start address for the corresponding field. For example: |
0x80 | TG_ADDR_MODE_WR | 2 | 6 | Readable and Writeable | Address Pattern | Address mode for writes. Consists of 6 registers, where each register specifies the write address mode for the corresponding address field. Available address modes include (see Address Generator Modes for details): |
0xC0 | TG_RETURN_TO_START_ADDR | 1 | 1 | Readable and Writable | Address Pattern | If set to 1, specifies to return to start address in each loop. If set to 0, specifies to resume the address pattern from where the previous loop left off. |
0x84 | TG_RAND_SEQ_ADDRS_RD | Readable and Writeable | Address Pattern | Number of times to increment sequentially on the random base address before generating a new random write address for reads. | ||
0x88 | TG_PASS | 1 | 1 | Read Only | Status | A value of 1 indicates that the traffic generator passed at the end of all test stages. |
0x8C | TG_FAIL | 1 | 1 | Read Only | Status | A value of 1 indicates that the traffic generator failed at the end of all test stages. |
0x90 | TG_FAIL_COUNT_L | 32 | 1 | Read Only | Status | The number of failed reads (lower 32 bits). |
0x94 | TG_FAIL_COUNT_H | 32 | 1 | Read Only | Status | The number of failed reads (upper 32 bits). |
0x98 | TG_FIRST_FAIL_ADDR_L | 32 | 1 | Read Only | Status | The address of the first failed read (lower 32 bits). |
0x9C | TG_FIRST_FAIL_ADDR_H | 32 | 1 | Read Only | Status | The address of the first failed read (upper 32 bits). |
0xA0 | TG_TOTAL_READ_COUNT_L | 32 |