External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents

3.2.1. Intel® Stratix® 10 EMIF DQS Tracking

DQS tracking tracks read capture clock/strobe timing variation over time, for improved read capture I/O timing. This feature takes sufficient samples to confirm the variation and adjust the DQS-enable position to maintain adequate operating margins.

DQS tracking is enabled for QDRII/II+/II+ Xtreme, QDR-IV, and RLDRAM 3 protocols; it is not available for DDR3 and DDR4 protocols. For QDRII/II+/II+ Xtreme, QDR-IV, and RLDRAM 3, DQS tracking does not need a specific command to initiate tracking, because the read capture clock/strobe is free running. Tracking happens constantly and automatically when the circuitry is enabled.

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