External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public
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13.7.2.7.2. Debugging Address and Command Leveling Calibration Failure

  1. In each rank, verify that CS#, CAS#/A15, and DQS/DQSn are connected correctly from the FPGA to the memory device.
    • In a non-clamshell configuration, the algorithm only checks if the DQS0/DQS0n in each rank are toggling.
    • In a clamshell configuration, the algorithm checks if all the DQS/DQSn are toggling.
  2. Try nondefault I/O settings for address and command and memory clock. Perform board simulation with IBIS models to determine the best settings for your design.