External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022

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Document Table of Contents Driver Margining Tab

The Driver Margining feature lets you measure margins on your memory interface using a driver with predefined traffic patterns. Margins measured with this feature are expected to be smaller than those measured during calibration, because this traffic pattern is longer than the ones run during calibration, and is intended to stress the interface.

Driver Margining is supported only when a memory interface meets all of the following criteria:

  • Has a TG IP (altera_emif_tg_avl) connected to it (that is, not the configurable traffic generator).
  • Does not have ECC enabled.
  • Has ISSPs enabled in the project’s .qsf file.

To run driver margining, click the Run Driver Margining button at the top left corner of the tab. The toolkit then measures margins for DQ read, DQ write, and DM. The process usually takes a few minutes, depending on the margin size, the interface size, and the duration of the driver tests. The test results are displayed in the table when the test is completed.

Figure 147. Driver Margining Tab

Note: Reports can also be viewed graphically; for information, refer to Viewing Diagrams in Eye Viewer .