External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public
Document Table of Contents
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13.7.2.7.3. Debugging Address and Command Deskew Failure

  1. Determine which pins are failing. And then:
    • If only some pins are failing, determine whether there is a connectivity problem on the failing net. Also check whether the failing net has the proper termination to VTT. Refer to the Board Design Guidelines section for your memory protocol in this user guide for recommended termination and decoupling requirements.
    • If all the pins are failing, verify connectivity on the PAR pin and the ALERT# pin. All the address and command pins fail this calibration stage if the memory device is not receiving the PARITY bit, or if the FPGA is not receiving the ALERT# signal from the memory device, or if the FPGA is not receiving the ALERT# signal from the memory device. Verify that the ALERT# signal is pulled up to 1.2V.
  2. Verify whether the memory clock is toggling at the correct frequency.
  3. Verify that the memory device is powered.
  4. Try with nondefault I/O settings for address and command and memory clock. Perform board simulation with IBIS models to determine the best settings for your design.