External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents Address Generator MSB Indices

You can specify a most significant bit (MSB) index with the TG_ADDR_FIELD_MSB_INDEX registers, to tie each address generator to a bit range in the generated address.

Because the MSB index for the uppermost field is implied to be at the MSB of the overall address, it is automatically assigned to AMM_WORD_ADDRESS_WIDTH-1 and does not have a configuration register. Writing to the word address (TG_ADDR_FIELD_MSB_INDEX + n) specifies the MSB index for field n. The system derives the address field widths from the values of the TG_ADDR_FIELD_MSB_INDEX registers. The difference between a field’s MSB index setting and the previous field’s MSB index setting is the field width.

For example, if field 0 has an MSB index of 5 and field 1 has an MSB index of 9, field 0 will span bits 0-5 (inclusive) and field 1 will span bits 6-9 (inclusive), giving field 0 a width of 6 and field 1 a width of 4.

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