External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public
Document Table of Contents
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4.1.5.3. pll_ref_clk for RLDRAM 3

PLL reference clock input

Table 141.  Interface: pll_ref_clkInterface type: Clock Input
Port Name Direction Description
pll_ref_clk Input PLL reference clock input